s71jl064ha0bfw62 Advanced Micro Devices, s71jl064ha0bfw62 Datasheet - Page 4

• Manufacturer Part Number: s71jl064ha0bfw62
• Description: Stacked Multi-chip Product Mcp Flash Memory And Psram Cmos 3.0volt-only, Simultaneous Operation Flash Memories And Static Ram/pseudo-static Ram
• Manufacturer: Advanced Micro Devices

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . 73
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .73
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 74
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 77
Erase And Programming Performance . . . . . . . .88
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 88
Functional Description . . . . . . . . . . . . . . . . . . . . . 89
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 90
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 90
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .92
4
DQ3: Sector Erase Timer ..................................................................................71
Zero-Power Flash ...............................................................................................75
Test Conditions ...................................................................................................76
Switching Waveforms ........................................................................................76
Read-Only Operations ......................................................................................77
Hardware Reset (RESET#) .............................................................................. 78
Word/Byte Configuration (BYTE#) ............................................................. 78
Erase and Program Operations ..................................................................... 80
Temporary Sector Unprotect ........................................................................ 84
Alternate CE# Controlled Erase and Program Operations ................. 86
Recommended DC Operating Conditions ................................................ 90
Capacitance (f=1MHz, T
DC and Operating Characteristics ................................................................ 91
Read/Write Charcteristics (V
Data Retention Characteristics ..................................................................... 92
Timing Diagrams ..................................................................................................93
Table 12. Write Operation Status ......................................... 72
Figure 8. Maximum Negative Overshoot Waveform ................. 73
Figure 9. Maximum Positive Overshoot Waveform .................. 73
Wireless (W) Devices ...................................................................................73
Industrial (I) Devices ......................................................................................73
V
Table 13. CMOS Compatible ................................................ 74
Figure 10. I
Sleep Currents).................................................................. 75
Figure 11. Typical ICC1 vs. Frequency................................... 75
Figure 12. Test Setup ........................................................ 76
Table 14. Test Specifications ............................................... 76
Table 15. Key To Switching Waveforms ................................ 76
Figure 13. Input Waveforms and Measurement Levels............. 76
Figure 14. Read Operation Timings ....................................... 77
Figure 15. Reset Timings..................................................... 78
Figure 16. BYTE# Timings for Read Operations ...................... 79
Figure 17. BYTE# Timings for Write Operations ...................... 79
Figure 18. Program Operation Timings .................................. 81
Figure 19. Accelerated Program Timing Diagram .................... 81
Figure 20. Chip/Sector Erase Operation Timings ..................... 82
Figure 21. Back-to-back Read/Write Cycle Timings ................. 82
Figure 22. Data# Polling Timings (During Embedded Algorithms) .
83
Figure 23. Toggle Bit Timings (During Embedded Algorithms) .. 83
Figure 24. DQ2 vs. DQ6 ...................................................... 84
Figure 25. Temporary Sector Unprotect Timing Diagram.......... 84
Figure 26. Sector/Sector Block Protect and Unprotect Timing
Diagram............................................................................ 85
Figure 27. Alternate CE# Controlled Write (Erase/Program)
Operation Timings .............................................................. 87
Table 16. Word Mode ......................................................... 89
Table 17. Byte Mode .......................................................... 89
CC
Supply Voltages ......................................................................................73
CC1
8 Mb SRAM (supplier 1)
Current vs. Time (Showing Active and Automatic
A
=25°C) ................................................................... 90
CC
=2.7-3.3V) ................................................ 92
A d v a n c e
Functional Description . . . . . . . . . . . . . . . . . . . . . 96
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 96
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 97
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 98
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
General Description . . . . . . . . . . . . . . . . . . . . . . . 103
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Absolute Maximum Ratings (See Note) . . . . . . 104
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 105
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 105
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
General Description . . . . . . . . . . . . . . . . . . . . . . 109
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Data Retention Waveforms ............................................................................ 95
Recommended DC Operating Conditions (Note 1) ............................... 97
Capacitance (f=1MHz, T
DC Operating Characteristics ....................................................................... 97
Read/Write Charcteristics (V
Data Retention Characteristics .....................................................................98
Timing Diagrams .................................................................................................99
Operating Characteristics (Over Specified Temperature Range) ......105
Timing Diagrams ................................................................................................107
I n f o r m a t i o n
Figure 28. Timing Waveform of Read Cycle(1) (address controlled,
CD#1=OE#=V
Figure 29. Timing Waveform of Read Cycle(2) (WE#=V
is low, ignore UB#/LB# timing) ........................................... 93
Figure 30. Timing Waveform of Write Cycle(1) (WE# controlled, if
BYTE# is low, ignore UB#/LB# timing)................................. 93
Figure 31. Timing Waveform of Write Cycle(2) (CE1# controlled, if
BYTE# is low, ignore UB#/LB# timing)................................. 94
Figure 32. Timing Waveform of Write Cycle(3) (UB#, LB#
controlled, BYTE# must be high) ......................................... 94
Figure 33. CE1# Controlled................................................. 95
Figure 34. CS2 Controlled ................................................... 95
Figure 35. Timing Waveform of Read Cycle(1) (address controlled,
CD#1=OE#=V
Figure 36. Timing Waveform of Read Cycle(2) (WE#=V
Figure 37. Timing Waveform of Write Cycle(1) (WE# controlled)...
100
Figure 38. Timing Waveform of Write Cycle(2) (CS# controlled) ...
100
Figure 39. Timing Waveform of Write Cycle(3) (UB#, LB#
controlled)...................................................................... 101
Figure 40. Data Retention Waveform.................................. 102
Figure 41. Functional Block Diagram .................................. 104
Table 18. Functional Description ........................................ 104
Table 19. Timing Test Conditions ....................................... 105
Table 20. Timings ............................................................ 106
Figure 42. Timing of Read Cycle (CE1# = OE# = V
= V
Figure 43. Timing Waveform of Read Cycle (WE# = V
Figure 44. Timing Waveform of Write Cycle (WE# Control) ... 108
Figure 45. Timing Waveform of Write Cycle (CE1# Control)... 108
Figure 46. Functional Block Diagram .................................. 110
IH
)............................................................................ 107
16 Mb pSRAM (supplier 2)
8 Mb pSRAM (supplier 2)
16 Mb SRAM (supplier 1)
IL
IL
, CS2=WE#=V
, CS2=WE#=V
A
=25°C) ................................................................... 97
CC
=2.7-3.3V) ................................................98
IH
IH
, UB# and/or LB#=V
, UB# and/or LB#=V
S71JLxxxHxx_00A0 February 24, 2004
IL
, WE# = CE2
IH
IL
IL
IH
IH
) ...... 107
) ........ 93
) ........ 99
, if BYTE#
) ...... 99