s71ws512ne0bfwzz Meet Spansion Inc., s71ws512ne0bfwzz Datasheet - Page 98

• Manufacturer Part Number: s71ws512ne0bfwzz
• Description: Stacked Multi-chip Product Mcp Flash Memoy And Psram Cmos 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory And Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

FUNCTIONAL DESCRIPTION
98
Power-up
Configuration Register
CR Set Sequence
Cycle #
2nd
3rd
4th
5th
6th
1st
This device supports asynchronous page read & normal write operation and syn-
chronous burst read & burst write operation for faster memory access and
features three kinds of power down modes for power saving as user configuable
option.
It is required to follow the power-up timing to start executing proper device
operation. Refer to POWER-UP Timing. After Power-up, the device defaults to
asynchronous page read & normal write operation mode with sleep power down
feature.
The Configuration Register (CR) is used to configure the type of device function
among optional features. Each selection of features is set through CR Set sequence
after Power-up. If CR Set sequence is not performed after power-up, the device
is configured for asynchronous operation with sleep power down feature as default
configuration
The CR Set requires total 6 read/write operation with unique address. Between
each read/write operation requires that device being in standby mode. Following
table shows the detail sequence.
The first cycle is to read from most significant address (MSB).
The second and third cycle are to write back the data (RDa) read by first cycle.
If the second or third cycle is written into the different address, the CR Set is
cancelled and the data written by the second or third cycle is valid as a normal
write operation.
The forth and fifth cycle is to write to MSB. The data of forth and fifth cycle is
don’t-care. If the forth or fifth cycle is written into different address, the CR Set
is also cancelled but write data may not be written as normal write operation.
The last cycle is to read from specific address key for mode selection. And read
data (RDb) is invalid.
Once this CR Set sequence is performed from an initial CR set to the other new
CR set, the written data stored in memory cell array may be lost. So, it should
perform the CR Set sequence prior to regular read/write operation if necessary
to change from default configuration.
Operation
Write
Write
Write
Write
Read
Read
128Mb pSRAM
P r e l i m i n a r y
7FFFFFh (MSB)
Address Key
Address
7FFFFFh
7FFFFFh
7FFFFFh
7FFFFFh
S71WS512NE0BFWZZ_00_A1 June 28, 2004
Read Data (RDa)
Read Data (RDb)
Data
RDa
RDa
X
X