s71ws512ne0bfwzz Meet Spansion Inc., s71ws512ne0bfwzz Datasheet - Page 83

• Manufacturer Part Number: s71ws512ne0bfwzz
• Description: Stacked Multi-chip Product Mcp Flash Memoy And Psram Cmos 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory And Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles
3. The device is in asynchronous mode with out wrap around.
4. DQ–DQ7 in data waveform indicate the order of data within a given 8-word address range, from lowest to
Notes:
1. Figure assumes 6 wait states for initial access and synchronous read.
2. The Set Configuration Register command sequence has been written with CR8=0; device will output RDY one
June 28, 2004 S71WS512NE0BFWZZ_00_A1
programmed from two cycles to seven cycles. Clock is set for active rising edge.
are inserted, and are indicated by RDY.
highest. Starting address in figure is the 4th address in range (AC).
cycle before valid data.
Addresses
Addresses
AVD#
AVD#
Data
Data
OE#
CE#
RDY
OE#
CLK
CE#
RDY
CLK
t AVC
Hi-Z
t ACS
Hi-Z
t AVC
t ACS
t CR
t ACH
AC
t CR
1
t ACH
t CES
Aa
Figure 17. Linear Burst with RDY Set One Cycle Before Data
1
Figure 16. Eight-word Linear Burst without Wrap Around
t CES
t AVD
A d v a n c e
t AVD
2
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP)
7
t OE
cycles for initial access shown.
2
6
3
wait cycles for initial access shown.
t IACC
t IACC
3
4
I n f o r m a t i o n
t OE
4
5
t RACC
5
6
t RACC
7
6
t RDYS
t RDYS
DC
Da
t BDH
DD
t BDH
Da+1
t BACC
t BACC
DE
Da+2
DF
Da+3
D10
D13
t CEZ
t OEZ
Da + n
t RACC
Hi-Z
Hi-Z
83