s71ws512ne0bfwzz Meet Spansion Inc., s71ws512ne0bfwzz Datasheet - Page 26

• Manufacturer Part Number: s71ws512ne0bfwzz
• Description: Stacked Multi-chip Product Mcp Flash Memoy And Psram Cmos 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory And Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

26
Simultaneous Read/Write Operations with Zero Latency
Writing Commands/Command Sequences
Accelerated Program/Erase Operations
This device is capable of reading data from one bank of memory while program-
ming or erasing in another bank of memory. An erase operation may also be
suspended to read from or program to another location within the same bank
(except the sector being erased).
be initiated for simultaneous operation with zero latency. Refer to the DC Char-
acteristics table for read-while-program and read-while-erase current
specifications.
The device has the capability of performing an asynchronous or synchronous
write operation. While the device is configured in Asynchronous read it is able to
perform Asynchronous write operations only. CLK is ignored when the device is
configured in the Asynchronous mode. When in the Synchronous read mode con-
figuration, the device is able to perform both Asynchronous and Synchronous
write operations. CLK and AVD# induced address latches are supported in the
Synchronous programming mode. During a synchronous write operation, to write
a command or command sequence (which includes programming data to the de-
vice and erasing sectors of memory), the system must drive AVD# and CE# to
V
CE# to V
chronous write operation, the system must drive CE# and WE# to V
to V
on the last falling edge of WE# or CE#, while data is latched on the 1st rising
edge of WE# or CE# (see
An erase operation can erase one sector, multiple sectors, or the entire device.
Table 12
dress space is divided into sixteen banks: Banks 1 through 14 contain only 64
Kword sectors, while Banks 0 and 15 contain both 16 Kword boot sectors in ad-
dition to 64 Kword sectors. A “bank address” is the set of address bits required
to uniquely select a bank. Similarly, a “sector address” is the address bits re-
quired to uniquely select a sector.
I
write mode.
chronous”
operations.
Unlock Bypass Mode
The device features an Unlock Bypass mode to facilitate faster programming.
Once the device enters the Unlock Bypass mode, only two write cycles are re-
quired to program a set of words, instead of four. See the
Command
The device offers accelerated program and accelerated chiperase operations
through the ACC function. ACC is intended to allow faster manufacturing
throughput at the factory and not to be used in system operations.
If the system asserts V
aforementioned Unlock Bypass mode and uses the higher voltage on the input to
reduce the time required for program and erase operations. The system can then
use the Write Buffer Load command sequence provided by the Unlock Bypass
mode. Note that if a “Write-to-Buffer-Abort Reset” is required while in Unlock By-
CC2
IL
, and OE# to V
IH
in
when providing an address, command, and data. Addresses are latched
“DC Characteristics”
IL
indicates the address space that each sector occupies. The device ad-
, and OE# to V
Sequence" section for more details.
contain timing specification tables and timing diagrams for write
“AC Characteristics—Synchronous”
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004
IH
when providing an address to the device, and drive WE# and
HH
IH
Table
A d v a n c e
on this input, the device automatically enters the
when writing commands or data. During an asyn-
represents the active current specification for the
16).
Figure 31
shows how read and write cycles may
I n f o r m a t i o n
and
“AC Characteristics—Asyn-
"Unlock Bypass
IL
and OE#