AM29DL323GB120PCI Meet Spansion Inc., AM29DL323GB120PCI Datasheet
AM29DL323GB120PCI
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AM29DL323GB120PCI Summary of contents
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Am29DL32xG Data Sheet This product has been retired and is not recommended for designs. For new and current designs, S29JL032H (for TSOP packages) and S29PL032J (for FBGA packages) supersede AM29DL32xG as the factory-recommended migration path. Please refer to each respective ...
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DATA SHEET Am29DL32xG 32 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory This product has been retired and is not recommended for designs. For new and current designs, S29JL032H (for TSOP packages) and ...
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GENERAL DESCRIPTION The Am29DL32xG family consists of 32 megabit, 3.0 volt-only flash memor y devices, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears ...
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TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . ...
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PRODUCT SELECTOR GUIDE Part Number Speed Rating Standard Voltage Range: V Max Access Time (ns) CE# Access (ns) OE# Access (ns) BLOCK DIAGRAM A20–A0 RY/BY# A20–A0 RESET# STATE CONTROL WE# & CE# COMMAND BYTE# REGISTER WP#/ACC ...
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CONNECTION DIAGRAMS A15 1 A14 2 A13 3 A12 4 A11 5 A10 A19 9 A20 10 WE# 11 RESET WP#/ACC 14 RY/BY# 15 A18 16 A17 ...
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CONNECTION DIAGRAMS A6 A13 WE# A3 RY/BY Special Package Handling Instructions Special handling is required for Flash Memory prod- ucts in molded packages (TSOP, BGA, PLCC, SSOP ...
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PIN DESCRIPTION A20– Addresses DQ14–DQ0 = 15 Data Inputs/Outputs DQ15/A-1 = DQ15 (Data Input/Output, word mode), A-1 (LSB Address Input, byte mode) CE# = Chip Enable OE# = Output Enable WE# = Write Enable WP#/ACC = Hardware Write ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Am29DL32xG DEVICE NUMBER/DESCRIPTION Am29DL32xG 32 Megabit ( ...
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Valid Combinations for FBGA Packages Order Number Package Marking AM29DL322GT70, D322GT70V, AM29DL322GB70 D322GB70V AM29DL323GT70, D323GT70V, AM29DL323GB70 D323GB70V AM29DL324GT70, D324GT70V, AM29DL324GB70 D324GB70V AM29DL322GT90, D322GT90V, AM29DL322GB90 D322GB90V WDI, AM29DL323GT90, D323GT90V, WDIN, AM29DL323GB90 D323GB90V WDF AM29DL324GT90, D324GT90V, AM29DL324GB90 D324GB90V AM29DL322GT120, D322GT12V, AM29DL322GB120 D322GB12V ...
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DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch ...
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Each bank remains enabled for read access until the command register contents are altered. See “Requirements for Reading Array Data” for more information. Refer to the AC Read-Only Operations table for timing specifications and ...
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While in sleep mode, output data is latched and always available to the system the DC Characteristics table represents the CC5 automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a ...
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Sector Address Sector SA0 000000xxx SA1 000001xxx SA2 000010xxx SA3 000011xxx SA4 000100xxx SA5 000101xxx SA6 000110xxx SA7 000111xxx SA8 001000xxx SA9 001001xxx SA10 001010xxx SA11 001011xxx SA12 001100xxx SA13 001101xxx SA14 001110xxx SA15 001111xxx SA16 010000xxx SA17 010001xxx SA18 ...
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Table 3. Top Boot Sector Addresses (Continued) Sector Address Sector SA48 110000xxx SA49 110001xxx SA50 110010xxx SA51 110011xxx SA52 110100xxx SA53 110101xxx SA54 110110xxx SA55 110111xxx SA56 111000xxx SA57 111001xxx SA58 111010xxx SA59 111011xxx SA60 111100xxx SA61 111101xxx SA62 111110xxx ...
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Sector Address Sector SA0 000000000 SA1 000000001 SA2 000000010 SA3 000000011 SA4 000000100 SA5 000000101 SA6 000000110 SA7 000000111 SA8 000001xxx SA9 000010xxx SA10 000011xxx SA11 000100xxx SA12 000101xxx SA13 000110xxx SA14 000111xxx SA15 001000xxx SA16 001001xxx SA17 001010xxx SA18 ...
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Table 5. Bottom Boot Sector Addresses (Continued) Sector Address Sector SA39 100000xxx SA40 100001xxx SA41 100010xxx SA42 100011xxx SA43 100100xxx SA44 100101xxx SA45 100110xxx SA46 100111xxx SA47 101000xxx SA48 101001xxx SA49 101010xxx SA50 101011xxx SA51 101100xxx SA52 101101xxx SA53 101110xxx ...
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Autoselect Mode The autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equip- ment to automatically match a device to be pro- grammed with ...
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Sector/Sector Block Protection and Unprotection (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see ...
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It is possible to determine whether a sector is pro- tected or unprotected. See the Autoselect Mode sec- tion for details. Write Protect (WP#) The Write Protect function provides a hardware method of protecting certain boot sectors without using V ...
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START PLSCNT = 1 RESET Wait 1 μs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with ...
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Secured Silicon Sector Flash Memory Region The Secured Silicon Sector feature provides a 256-byte Flash memory region that enables perma- nent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector uses a Secured Silicon Sector Indicator Bit ...
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V and power-down transitions, or from system noise. Low V Write Inhibit CC When V is less than V , the ...
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Addresses Addresses (Word Mode) (Byte Mode) 1Bh 36h 1Ch 38h 1Dh 3Ah 1Eh 3Ch 1Fh 3Eh 20h 40h 21h 42h 22h 44h 23h 46h 24h 48h 25h 4Ah 26h 4Ch Addresses Addresses (Word Mode) (Byte Mode) 27h 4Eh 28h 50h ...
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Table 13. Primary Vendor-Specific Extended Query Addresses Addresses (Word Mode) (Byte Mode) 40h 80h 41h 82h 42h 84h 43h 86h 44h 88h 45h 8Ah 46h 8Ch 47h 8Eh 48h 90h 49h 92h 4Ah 94h 4Bh 96h 4Ch 98h 4Dh 9Ah ...
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See the Erase Suspend/Erase Resume Commands sec- tion for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high ...
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Table 14 shows the address and data requirements for the byte program command se- quence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and ad- dresses are no longer latched. ...
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When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the sta- tus of ...
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After an erase-suspended program operation is com- plete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard Byte Program operation. ...
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Command Sequence (Note 1) Addr Read (Note 6) 1 Reset (Note 7) 1 XXX Word 555 Manufacturer ID 4 Byte AAA Word 555 Device ID 4 Byte AAA Secured Silicon Sector Word 555 Factory Protect (Note 4 Byte AAA 9) ...
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WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 15 and the following subsections describe the function of these bits. DQ7 and DQ6 each ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since ...
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DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Erase Suspended Sector Erase-Suspend- Erase Read Suspend Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied ...
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DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description I Input Load Current Input Load Current LIT I Output Leakage Current LO V Active Read Current CC I CC1 (Notes Active Write Current (Notes ...
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DC CHARACTERISTICS Zero-Power Flash 500 1000 Note: Addresses are switching at 1 MHz Figure 9. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...
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TEST CONDITIONS Device Under Test C 6.2 kΩ L Note: Diodes are IN3064 or equivalent Figure 11. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 3.0 V 1.5 V Input 0.0 V Figure 12. Input Waveforms ...
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AC CHARACTERISTICS Read-Only Operations Parameter JEDEC Std. Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to Output ...
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AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read Mode (See Note) t RESET# Pulse Width RP ...
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AC CHARACTERISTICS Word/Byte Configuration (BYTE#) Parameter JEDEC Std Description t /t CE# to BYTE# Switching Low or High ELFL ELFH t BYTE# Switching Low to Output HIGH Z FLQZ t BYTE# Switching High to Output Active FHQV CE# OE# BYTE# ...
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AC CHARACTERISTICS Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS t Address Setup Time to OE# low during toggle bit polling ASO t t ...
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AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE# OE# WE Data RY/BY VCS Notes program address program data Illustration shows device in word ...
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AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE Data 55h RY/BY# t VCS V CC Notes sector address (for Sector Erase Valid ...
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AC CHARACTERISTICS t WC Valid PA Addresses t AH CE# OE WE# t WPH Valid Data In WE# Controlled Write Cycle Figure 20. Back-to-back Read/Write Cycle Timings t RC Addresses VA t ACC t ...
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AC CHARACTERISTICS Addresses CE# t OEH WE# OE Valid Data DQ6/DQ2 RY/BY# Note Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read ...
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AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR Rise and Fall Time (See Note) VHH HH RESET# Setup Time for Temporary Sector t RSP Unprotect RESET# Hold ...
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AC CHARACTERISTICS RESET# SA, A6, A1, A0 Sector/Sector Block Protect or Unprotect Data 60h 1 µs CE# WE# OE# * For sector protect For sector unprotect, A6 ...
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AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time ELAX Data Setup ...
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AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation ...
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ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Program Time Accelerated Byte/Word Program Time Word Program Time Byte Mode Chip Program Time (Note 3) Word Mode Notes: 1. Typical program and erase times assume the following ...
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PHYSICAL DIMENSIONS FBD063—63-ball Fine-Pitch Ball Grid Array (FBGA December 4, 2006 25686B10 Am29DL32xG Dwg rev AF; 10/99 51 ...
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PHYSICAL DIMENSIONS FBD048—Fine-Pitch Ball Grid Array FBD 048 6. 12.00 mm PACKAGE 1.20 0.20 0.94 0.84 12.00 BSC 6.00 BSC 5.60 BSC 4.00 BSC 0.25 0.30 0.35 0.80 BSC 0.40 BSC ...
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PHYSICAL DIMENSIONS TS 048—Thin Small Outline Package December 4, 2006 25686B10 Am29DL32xG Dwg rev AA; 10/99 53 ...
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PHYSICAL DIMENSIONS LAA064—64-ball Fortified Ball Grid Array ( package BGA) Am29DL32xG 25686B10 December 4, 2006 ...
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REVISION SUMMARY Revision A (November 7, 2001) Global Initial release. This device replaces the AM29DL32xD. Revision B (July 31, 2002) Global Added LAA064 package. Ordering Information Corrected package marking for FBGA. AC Characteristics Added 70 ns speed grade to Test ...
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Revision (February 9, 2005) Connection Diagrams Updated the 64-ball FBGA diagram. Pin Description Added RFU to the list of pins Revision (June 7, 2005) Cover sheet and title page Modified notation to superseding documents. ...