s71ws512ne0bfwzz Meet Spansion Inc., s71ws512ne0bfwzz Datasheet - Page 59

• Manufacturer Part Number: s71ws512ne0bfwzz
• Description: Stacked Multi-chip Product Mcp Flash Memoy And Psram Cmos 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory And Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

June 28, 2004 S71WS512NE0BFWZZ_00_A1
Sector Erase Command Sequence
erase. The Embedded Erase algorithm automatically preprograms and verifies the
entire memory for an all zero data pattern prior to electrical erase. The system is
not required to provide any controls or timings during these operations. The
"Command Definition
ments for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read
mode and addresses are no longer latched. The system can determine the status
of the erase operation by using DQ7 or DQ6/DQ2. Refer to
tus”
Any commands written during the chip erase operation are ignored. However,
note that a hardware reset immediately terminates the erase operation. If that
occurs, the chip erase command sequence should be reinitiated once that bank
has returned to reading array data, to ensure data integrity.
The host system may also initiate the chip erase command sequence while the
device is in the unlock bypass mode. The command sequence is two cycles in
length instead of six cycles.
Figure 4
gram Operations @ V
Sector erase is a six bus cycle operation or, in the unlock bypass mode, a four-
cycle operation. The sector erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock cycles are
written, and are then followed by the address of the sector to be erased, and the
sector erase command. The
address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Em-
bedded Erase algorithm automatically programs and verifies the entire memory
for an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of no less than
50 µs occurs. During the time-out period, additional sector addresses and sector
erase commands may be written. Loading the sector erase buffer may be done
in any sequence, and the number of sectors may be from one sector to all sectors.
The time between these additional cycles must be less than 50 µs, otherwise era-
sure may begin. Any sector erase address and command following the exceeded
time-out may or may not be accepted. It is recommended that processor inter-
rupts be disabled during this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase command is written. Any
command other than Sector Erase or Erase Suspend during the time-out period
resets that bank to the read mode. The system must rewrite the command se-
quence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out
(See the
edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading
array data and addresses are no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read data from the non-erasing
bank. The system can determine the status of the erase operation by reading
for information on these status bits.
illustrates the algorithm for the erase operation. Refer to the
"DQ3: Sector Erase
A d v a n c e
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP)
IO
Summary" section shows the address and data require-
= 1.8
I n f o r m a t i o n
"Command Definition
Timer" section.) The time-out begins from the rising
V" section for parameters and timing diagrams.
Summary" section shows the
“Write Operation Sta-
"Erase/Pro-
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