s71ws512ne0bfwzz Meet Spansion Inc., s71ws512ne0bfwzz Datasheet - Page 53

• Manufacturer Part Number: s71ws512ne0bfwzz
• Description: Stacked Multi-chip Product Mcp Flash Memoy And Psram Cmos 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory And Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

June 28, 2004 S71WS512NE0BFWZZ_00_A1
CR BIt
CR15
CR14
CR13
CR12
CR11
CR10
CR9
CR8
CR7
CR6
CR3
CR2
CR1
CR0
Configuration Register
Reset Command
case, the RDY pin will always indicate that the device is ready to handle a new
transaction when low.
Table 16
for various device functions.
Writing the reset command resets the banks to the read or erase-suspend-read
mode. Address bits are don’t cares for this command.
The reset command may be written between the sequence cycles in an erase
command sequence before erasing begins. This resets the bank to which the sys-
tem was writing to the read mode. Once erasure begins, however, the device
ignores reset commands until the operation is complete.
Programmable
Notes: Device will be in the default state upon power-up or hardware reset.
Burst Length
RDY Polarity
Set Internal
Read Mode
Burst Wrap
Set Device
Wait State
Frequency
Sequence
Boundary
Crossing
Function
Around
Clock
Burst
Clock
RDY
shows the address bits that determine the configuration register settings
A d v a n c e
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP)
Settings (Binary)
101 = Data is valid on the 7th active CLK edge after addresses are latched (default)
000 = Data is valid on the 2nd active CLK edge after addresses are latched
001 = Data is valid on the 3rd active CLK edge after addresses are latched
010 = Data is valid on the 4th active CLK edge after addresses are latched
011 = Data is valid on the 5th active CLK edge after addresses are latched
100 = Data is valid on the 6th active CLK edge after addresses are latched
1 = Internal clock switches at full frequency of the external clock (default)
Table 16. Configuration Register
1 = Burst starts and data is output on the rising edge of CLK (default)
0 = Burst starts and data is output on the falling edge of CLK
I n f o r m a t i o n
1 = With extra boundary crossing latency (default)
0 = Synchronous Read (Burst Mode) Enabled
0 = RDY active one clock cycle before data
0 = No extra boundary crossing latency
1 = RDY signal is active high (default)
1 = Sequential Burst Order (default)
(All other bit settings are reserved)
1 = RDY active with data (default)
1 = Asynchronous Mode (default)
1 = Wrap Around Burst (default)
0 = Reserved for Future Use
0 = Reserved for Future Use
011 = 16-Word Linear Burst
100 = 32-Word Linear Burst
0 = RDY signal is active low
000 = Continuous (default)
010 = 8-Word Linear Burst
0 = No Wrap Around Burst
110 = Reserved
111 = Reserved
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