zl50400 Zarlink Semiconductor, zl50400 Datasheet - Page 96

• Manufacturer Part Number: zl50400
• Description: Lightly Managed/unmanaged 9-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

12.3.7.13
CPU Address:h610
Accessed by CPU (R/W)
In slot time (512 bit time). LHB packet will be sent out to the remote device if no other packet is transmitted in half
this period. The receiver will trigger LHB timeout interrupt if not receiving any good packet in this period.
12.3.7.14
CPU Address:h611, h612
Accessed by CPU (R/W)
The LHB frame uses MAC control frame format (same as flow control frame.) The register here defines the
operation code (we recommend h00-12).
12.3.7.15
CPU Address:h613, h614
Accessed by CPU (R/W)
The registers define the operation code if MAC control frame is forced out by processor.
12.3.7.16
I²C Address 0BF, CPU Address:h620
Accessed by CPU and I²C (R/W)
12.3.7.17
I²C Address 0C0, CPU Address:h621
Accessed by CPU and I²C (R/W)
12.3.7.18
I²C Address 0C1, CPU Address:h622
Accessed by CPU and I²C (R/W)
Bits [7:0]
Bits [7:0]
Bits [7:0]
LHBTimer – Link Heart Beat Timeout Timer
LHBReg0, LHBReg1 - Link Heart Beat OpCode
fMACCReg0, fMACCReg1 - MAC Control Frame OpCode
FCB Base Address Register 0
FCB Base Address Register 1
FCB Base Address Register 2
FCB Base address bit 7:0 (Default 0)
FCB Base address bit 15:8 (Default 0x60)
FCB Base address bit 23:16 (Default 0)
Zarlink Semiconductor Inc.
ZL50400
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Data Sheet