zl50400 Zarlink Semiconductor, zl50400 Datasheet

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... Per queue traffic shaper on uplink port 2 C EEPROM ZL50400 MII 9-Port 10/100M Ethernet Switch RMII / MII / GPSI Quad Quad 10/100 10/100 PHY PHY Figure 1 - System Block Diagram 1 Zarlink Semiconductor Inc. ZL50400 Data Sheet January 2005 Ordering Information 208 Pin LBGA -40GC to +85GC 10/100 PHY ...

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... Backpressure flow control for Half Duplex ports • Hardware auto-negotiation through MII management interface (MDIO) for Ethernet ports • Built-in reset logic triggered by system malfunction • Built-In Self Test for internal SRAM • IEEE-1149.1 (JTAG) test port ZL50400 2 Zarlink Semiconductor Inc. Data Sheet ...

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... The ZL50400 provides the ability to monitor a link, detect a simple link failure, and provide notification of the failure to the CPU. The CPU can then failover that link to an alternate link. The ZL50400 supports groups of port trunking/load sharing. Each group can contain ports. Port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth ...

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... Multicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3 Frame Forwarding To and From CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.0 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 Search Engine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 Basic Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3 Search, Learning, and Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3.1 MAC Search 5.3.2 Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3.3 Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.4 MAC Address Filtering 5.5 Protocol Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.6 Logical Port Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.7 Quality of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 ZL50400 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...

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... MMAC Reference Clock (REF_CLK) speed requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1.4 JTAG Test Clock (TCK) speed requirements 10.2 Clock Generation 10.2.1 MDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2.2 SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2.3 Ethernet Interface Clocks 11.0 Hardware Statistics Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.1 Hardware Statistics Counters List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.2 IEEE 802.3 HUB Management (RFC 1516 11.2.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2.1.1 ReadableOctet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2.1.2 ReadableFrame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.2.1.3 FCSErrors 11.2.1.4 AlignmentErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 ZL50400 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...

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... CRCAlignErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.4.1.6 UndersizePkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.4.1.7 OversizePkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.4.1.8 Fragments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.4.1.9 Jabbers 11.4.1.10 Collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.4.1.11 Packet Count for Different Size Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.5 Miscellaneous Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 12.0 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.1 ZL50400 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.2 Directly Accessed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.2.1 INDEX_REG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.2.2 DATA_FRAME_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.2.3 CONTROL_FRAME_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.2.4 COMMAND&STATUS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.2.5 Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.2.6 Control Command Frame Buffer1 Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.2.7 Control Command Frame Buffer2 Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12 ...

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... RDRC1 – WRED Rate Control 12.3.6.7 RDRC2 – WRED Rate Control 12.3.6.8 SFCB – Share FCB Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3.6.9 C1RS – Class 1 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3.6.10 C2RS – Class 2 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3.6.11 C3RS – Class 3 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.3.6.12 AVPML – VLAN Tag Priority Map ZL50400 Table of Contents 7 Zarlink Semiconductor Inc. Data Sheet ...

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... Address) Port Mirroring Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 12.3.8.1 MIRROR CONTROL – Port Mirror Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 12.3.8.2 MIRROR_DEST_MAC[5:0] – Mirror Destination MAC Address 0 100 12.3.8.3 MIRROR_SRC _MAC[5:0] – Mirror Source MAC Address 0 100 12.3.8.4 RMAC_MIRROR0 – RMAC Mirror 100 ZL50400 Table of Contents 8 Zarlink Semiconductor Inc. Data Sheet ...

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... DA – Dead or Alive Register 114 13.0 Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 13.1 Absolute Maximum Ratings 115 13.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 13.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 13.4 AC Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13.4.1 Typical Reset & Bootstrap Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13.4.2 Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 ZL50400 Table of Contents 9 Zarlink Semiconductor Inc. Data Sheet ...

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... I²C Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 13.4.7 Serial Interface Setup Timing 123 13.4.8 JTAG (IEEE 1149.1-2001 124 14.0 Document History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.1 July 2003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.2 November 2003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.3 February 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.4 August 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.5 November 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ZL50400 Table of Contents 10 Zarlink Semiconductor Inc. Data Sheet ...

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... M2_RX M2_C M2_TX M3_RX M3_C 1.2 Power and Ground Distribution G7-10, H7-10, J7-10, K7-10 D5, D12, E4, E13, M4, M13, N5 D9, H4, H13, N7 ZL50400 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD TSTO TSTO TSTO TSTO TSTO UT7 UT9 ...

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... P4, R4, T4, N1, P1, R1, T1, J4, K3, K2, K1, F4, F3, G2, G1 K16, T15, T12, T9, T5, M[7:0]_CRS_DV Input T2, L1, H1 ZL50400 Active low signal Input signal Input signal with Schmitt-Trigger Output signal (Tri-State driver) Input & Output signal with Tri-State driver Weak internal pull-up (nominal 100K ohm) (refer to Section 1 ...

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... C16 M9_COL B16 M9_RXCLK F14, F13, G14, G13 M9_RXD[3:0] A16 M9_TXEN A15 M9_MTXCLK ZL50400 I/O Output, slew Ports [7:0] – Transmit Enable This pin also serves as a bootstrap pin. Output, slew Ports [7:0] – Transmit Data Bit [3:0] Input Ports[7:0] – Collision with pull-down Input or Output Ports[7:0] – ...

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... V CC M13, N5, G7-10, H7-10, J7-10 K7-10 Misc. D1 RESIN# C1 RESETOUT# F1 M_MDC F2 M_MDIO ZL50400 I/O Output [15:4] Reserved [3] EEPROM checksum is good [2] Initialization Completed [1] Memory Self Test in progress [0] Initialization started These pins also serve as bootstrap pins. Input JTAG - Test Data In with pull-up Input JTAG - Test Reset with pull-up Input ...

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... Bootstrap Pins (1= pull-up 0= pull-down) (See “Bootstrap Options” on page 19) D2 TSTOUT[0] D3, C2 TSTOUT[2:1] C3 TSTOUT[3] C5, C4, D4 TSTOUT[6:4] C6 TSTOUT[7] D7 TSTOUT[8] ZL50400 I/O Input RMAC Reference Clock Input MMAC Reference Clock with pull-up N/A Reserved. Leave unconnected. 1 Input (Reset Only) Enable Debounce of STROBE signal Pullup – Enabled Pulldown - Disabled Input (Reset Only) Reserved ...

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... K15, R15, R12, R9, M[7:0]_TXEN R5, R2, L2 External pull-up/down resistors are required on all bootstrap pins for proper operation. Recommend 10 K for pull-ups and 1 K for pull-downs. ZL50400 I/O Input (Reset Only) Module Detect Pullup: Enable. In this mode, the device will detect the existence of a PHY (for hot swap purpose) ...

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... Signal Mapping and Internal pull-up/Down Configuration The ZL50400 Fast Ethernet access ports (0-7) support 3 interface options: RMII, MII & GPSI. The table below summarizes the interface signals required for each interface and how they relate back to the Pin Symbol name shown in the “Ball Signal Description Table” on page 12. It also specifies whether the internal pull-up/down resistor is present for each pin in the specific operating mode ...

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... The ZL50400 Fast Ethernet uplink port (port 9) supports 1 interface option: MII. The table below summarizes the interface signals required for each interface, and how they relate back to the Pin Symbol name shown in “Ball Signal Description Table” on page 12. Fast Ethernet Uplink Port ...

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... Also, in unmanaged mode, an optional I the device at power-up or reset. TSTOUT[7] selects the EEPROM option. The ZL50400 supports module hotswap on all it's ports. This is enabled via TSTOUT[9]. When enabled, bootstrap pins M[7:0]_TXEN (ports 0-7) are used to specify the module type to support multiple ethernet interfaces during module hotswap ...

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... Default Switch Configuration and Initialization Sequence The ZL50400 will come out of reset in a default configuration, which will allow for basic L2 switching and automatic MAC address learning. In unmanaged mode, the default configuration will take effect immediately after reset. The default settings can be changed using the optional EEPROM. • ...

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... DiffServ EF code support disabled • No VLAN ID hashing • Per-port Defaults • FE Ports - Link heart beat disabled • CPU Port - 100M/Full Duplex/Flow Control - 8-byte header padding - per-source port buffer pool of 96 buffers, with flow control threshold of 48 buffers ZL50400 21 Zarlink Semiconductor Inc. Data Sheet ...

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... Frame Engine (FE) and the external physical device (PHY). It has five interfaces: MII, RMII, GPSI (only for 10M), Reverse MII, or Reverse GPSI (only for 10M). The RMAC of the ZL50400 device meets the IEEE 802.3 specification able to operate in either Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit upon collision for total transmissions ...

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... Frame Engine (FE) and the external physical device (PHY). The MMAC implements an MII interface. The MMAC of the ZL50400 device meets the IEEE 802.3 specification able to operate in 10 M/100 M either Half or Full Duplex mode with a back pressure/flow control mechanism. Furthermore, it will automatically retransmit upon collision for total transmissions ...

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... Heartbeat Packet Generation and Response The ZL50400 provides the ability to monitor a link and detect a simple link failure. The Link Heart Beat (LHB) packet generation module allows simultaneous tracking of all the RMAC ports. Periodically, a LHB message will be sent for each link when inactivity is detected with in a programmable time period reply is not received in a specified amount of time, the failover detection module will identify a point-to-point failure for that link ...

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... Register Configuration The ZL50400 has many programmable parameters, covering such functions as QoS weights, VLAN control, and port mirroring setup. In managed mode, the CPU interface provides an easy way of configuring these parameters. The parameters are contained in 8-bit configuration registers. The device allows indirect access to these registers, as follows: • ...

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... The speed of the serial interface limits management capability. For example, if the system is trying to implement port security, it would require a faster interface between the CPU and the ZL50400, such as the 8/16-bit interface or the serial + MII interface found on the managed device. 3.1.3 ...

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... Start Condition Generated by the master (in our case, the ZL50400). The bus is considered to be busy after the Start condition is generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line. Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I² ...

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... I²C protocol. The main difference is that there is no acknowledgment bit after each byte of data transferred. Debounce logic on the clock signal (STROBE) can be turned off to speedup command time bits are used to allow up to eight ZL50400 devices to share the same synchronous serial interface. The ID of each device can be setup by bootstrap. ...

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... STROBE- fall. 3.3.1 Write Command All registers in ZL50400 can be modified through this synchronous serial interface. Once the data has been sent, two extra STOBE clocks must be generated to indicate the end of the write command. The DATAIN line should be held high for these two pulses. ...

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... RMAC ports to map the 8 transmit priorities into 2 multicast queues, the 2 LSB are discarded. For the MMAC and CPU ports, to map the 8 transmit priorities into 4 multicast queues, the LSB is discarded. The priority mapping can be modified through memory configuration command. The multicast queue that is in FIFO format shares the ZL50400 30 Zarlink Semiconductor Inc. ...

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... Basic Flow Shortly after a frame enters the ZL50400 and is written to the Frame Data Buffer (FDB), the frame engine generates a Switch Request, which is sent to the search engine. The switch request consists of the first 64 bytes of the frame, which contain all the necessary information for the search engine to perform its task. When the search engine is done, it writes to the Switch Response Queue, and the frame engine uses the information provided in that queue for scheduling and forwarding ...

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... This feature filters unnecessary traffic, thereby providing intelligent control over traffic flows and broadcast traffic. MAC address filtering allows the ZL50400 to block an incoming packet to an interface when it sees a specified MAC address in either the source address or destination address of the incoming packet. For example, if your network is congested because of high utilization from a MAC address, you can filter all traffic transmitted from that address and restore network flow, while you troubleshoot the problem ...

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... Extensive core QoS mechanisms are built into the ZL50400 architecture to ensure policy enforcement and buffering of the ingress port, as well as weighted fair-queue (WFQ) scheduling at the egress port. In the ZL50400, QoS-based policies sort traffic into a small number of classes and mark the packets accordingly. The QoS identifier provides specific treatment to traffic in different classes, so that different quality of service is provided to each class ...

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... Definition” on page 53). For example, ports 1-3 might be assigned to the Marketing VLAN, ports 4-6 to the Engineering VLAN, and ports 7-9 to the Administrative VLAN. The ZL50400 determines the VLAN membership of each packet by noting the port on which it arrives. From there, the ZL50400 determines which outgoing port(s) is/are eligible to transmit each packet, or whether the packet should be discarded. ...

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... The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of the destination port. 6.2 Frame Engine Details This section briefly describes the functions of each of the modules of the ZL50400 frame engine. 6.2.1 FCB Manager The FCB manager allocates FCB handles to incoming frames, and releases FCB handles upon frame departure. ...

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... Table 7 shows examples of QoS applications with three transmission priorities, but best effort (P0) traffic may form a fourth class with no bandwidth or latency assurances. MMAC port actually has four total transmission priorities. ZL50400 36 Zarlink Semiconductor Inc. ...

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... It is also possible to add a fourth class that has strict priority over the other three; if this class has even one frame to transmit, then it goes first. In the ZL50400, each RMAC port will support two total classes, and the MMAC port will support four classes. We will discuss the various modes of scheduling these classes in the next section ...

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... Although traffic shaping is not a primary function of the ZL50400, the chip does implement a shaper for every queue in the MMAC port. Our goal in shaping is to control the average rate of traffic exiting the ZL50400. If shaper is enabled, strict priority will be applied to that queue. The priority between two shaped queue is the same as in strict priority scheduling ...

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... Such a temporary region is necessary, because when the frame first enters the ZL50400, its destination port and class are as yet unknown, and so the decision to drop or not needs to be temporarily postponed. This ensures that every frame can be received first before subjecting them to the frame drop discipline after classifying ...

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... The resulting head-of-line blocking phenomenon means that quality of service cannot be assured with high confidence when flow control is enabled. On the other hand, the ZL50400 will still prioritize the received frame disregarding the outgoing port flow control capability frame is classified as high priority still subjected to the WRED, which means the no-loss on the high priority queue is not guaranteed ...

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... Xon is triggered when a port is currently being flow controlled, and all of that port’s reserved FDB slots have been released. Note that the ZL50400’s per-source-port FDB reservations assure that a source port that sends a single frame to a congested destination will not be flow controlled. ...

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... On the receiving side, the MAC will also monitor the activity. If there is no good packet received for more than 2X the set period, an alarm will be raised to the CPU. The LHB packet is only used by the ZL50400 to reset the timeout counter ignored otherwise (i.e. not passed on within the system). ...

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... Up to two ports can be setup as mirrored ports result, the traffic (both ingress and egress specific port can be monitored by setting up both mirrored ports. Once a port is setup as mirrored port, it cannot be used for regular traffic. The mirrored port can be any port in the ZL50400. 9.2 Using port mirroring for loop back To perform remote loop back test, port mirroring can be used to bounce back the packet to the source port to check the data path ...

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... Clocks 10.1 Clock Requirements 10.1.1 System Clock (SCLK) speed requirement SCLK is the primary clock for the ZL50400 device. The speed requirement is based on the system configuration. Below is a table for a few configuration. Configuration 6-9 ports 10/100M 1-5 ports 10/100M 10.1.2 RMAC Reference Clock (M_CLK) speed requirement M_CLK MHz clock used for the RMAC ports (ports 0-7). ...

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... Hardware Statistics Counters List ZL50400 hardware provides a full set of statistics counters for each Ethernet port. The CPU accesses these counters through the CPU interface. All hardware counters are rollover counters. When a counter rolls over, the CPU is interrupted, so that long-term statistics may be kept. The MAC detects all statistics, except for the delay exceed discard counter (detected by buffer manager) and the filtering counter (detected by queue manager) ...

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... Late Collision B[29] F-U Notation: X-Y Address in the contain memory X: Size and bits for the counter Y: D Word counter d: 24 bits counter bit [23: bits counter bit [31:24 bits counter bit [23:16] U1: 16 bits counter bit [15: bits counter bit [31:16] u: ZL50400 46 Zarlink Semiconductor Inc. Data Sheet ...

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... No collisions 11.2.1.4 AlignmentErrors Counts number of valid frames received with bad alignment (not byte-aligned). Frame size: No framing error No collisions ZL50400 > 64 bytes, < 1522 bytes if VLAN Tagged; (< 1518 bytes if not VLAN Tagged) (< BUF_LIMIT if enabled for this port) > 64 bytes, < 1522 bytes if VLAN Tagged; (< 1518 bytes if not VLAN Tagged) (< ...

Page 48

... Frame size: 11.2.1.9 LateEvents Counts number of collision events that occurred late (after LateEventThreshold = 64 bytes). Frame size: Events are also counted by collision counter ZL50400 > 64 bytes, > 1522 bytes if VLAN Tagged; (> 1518 bytes if not VLAN Tagged) (> BUF_LIMIT if enabled for this port) don’t care don’ ...

Page 49

... InDiscards Counts number of valid frames received which were discarded (i.e., filtered) by the forwarding process. 11.3.1.4 DelayExceededDiscards Counts number of frames discarded due to excessive transmit delay through the bridge. 11.3.1.5 MtuExceededDiscards Counts number of frames discarded due to excessive size. ZL50400 > Jabber 49 Zarlink Semiconductor Inc. Data Sheet ...

Page 50

... No collisions: 11.4.1.6 UndersizePkts Counts number of frames received with size less than 64 bytes. Frame size: No FCS error No framing error No collisions ZL50400 > 64 bytes, < 1522 bytes if VLAN Tagged; (< 1518 bytes if not VLAN Tagged) (< BUF_LIMIT if enabled for this port) < 64 bytes, 50 Zarlink Semiconductor Inc. Data Sheet ...

Page 51

... Jabbers Counts number of frames received with size exceeding maximum frame size and with bad FCS. Frame size: Framing error No collisions ZL50400 > 1522 bytes if VLAN Tagged; (> 1518 bytes if not VLAN Tagged) (> BUF_LIMIT if enabled for this port) don’t care don’t care < ...

Page 52

... Miscellaneous Counters In addition to the statistics groups defined in previous sections, the ZL50400 has other statistics counters for its own purposes. We have two counters for flow control – one counting the number of flow control frames received, and another counting the number of flow control frames sent. We also have two counters, one for unicast frames sent, and one for non-unicast frames sent. A broadcast or multicast frame qualifies as non-unicast. Furthermore, we have a counter called “ ...

Page 53

... Register Definition 12.1 ZL50400 Register Description Register 0. ETHERNET Port Control Registers (Substitute [n] with Port number (0..9)) ECR1Pn Port Control Register 1 for Port n ECR2Pn Port Control Register 2 for Port n ECR3Pn Port Control Register 3 for Port n ECR4Pn Port Control Register 4 for Port n BUF_LIMIT Frame Buffer Limit ...

Page 54

... AGETIME_LOW MAC Address Aging Time Low AGETIME_HIGH MAC Address Aging Time High SE_OPMODE Search Engine Operating Mode 5. Global QOS Control QOSC QOS Control Table 12 - Register Description (continued) ZL50400 CPU Addr Description (Hex) 229+2n 300 301 302 303 304 305 306 310+n ...

Page 55

... Priority WLPP76 Well Known Logic Port 6 and 7 Priority WLPE Well Known Logic Port Enable WLPFD Well Known Logic Port Force Discard Enable Table 12 - Register Description (continued) ZL50400 CPU Addr Description (Hex) 510 511 512 513 514 515 518 ...

Page 56

... MII Command Register 2 MIIC3 MII Command Register 3 MIID0 MII Data Register 0 MIID1 MII Data Register 1 USD One micro second divider DEVICE Device id and test Table 12 - Register Description (continued) ZL50400 CPU Addr Description (Hex) 570+2n 571+2n 590 591 592 593 594 595 ...

Page 57

... Address 0 MIRROR_SRC_MAC1 Mirror Source MAC Address 1 MIRROR_SRC_MAC2 Mirror Source MAC Address 2 MIRROR_SRC_MAC3 Mirror Source MAC Address 3 MIRROR_SRC_MAC4 Mirror Source MAC Address 4 Table 12 - Register Description (continued) ZL50400 CPU Addr Description (Hex) 60B 610 611 612 613 614 620 621 622 700 701 ...

Page 58

... TESTOUT0 Testmux Output [7:0] TESTOUT1 Testmux Output [15:8] MASK0 MASK Timeout 0 MASK1 MASK Timeout 1 MASK2 MASK Timeout 2 MASK3 MASK Timeout 3 MASK4 MASK Timeout 4 Table 12 - Register Description (continued) ZL50400 CPU Addr Description (Hex) 70B 70C 710 711 800+n 820+n 840+n 848 849 860+n 868 ...

Page 59

... Number [14:8] BM_RLSFF_CTRL Read control register BM_RLSFF_INFO0 Bm_rlsfifo_info[7:0] BM_RLSFF_INFO1 Bm_rlsfifo_info[15:8] BM_RLSFF_INFO2 Bm_rlsfifo_info[23:16] BM_RLSFF_INFO3 Bm_rlsfifo_info[31:24] BM_RLSFF_INFO4 Bm_rlsfifo_info[39:32] BM_RLSFF_INFO5 Fifo_cnt[2:0],Bm_rlsfifo_inf o[44:40] Table 12 - Register Description (continued) ZL50400 CPU Addr Description (Hex) E80-E82 E90+n EA0+n EA8 EA9 EAA EAB EAC EAD EB0+n EBA EBB EBC EBD ...

Page 60

... Frame status (Frame size, Source port #, VLAN tag) Frame Data (size should be in multiple of 8-byte) 12.2.4 COMMAND&STATUS Register • CPU interface commands and status (8 bits) • Address = 4 (read/write) • When the CPU writes to this register ZL50400 CPU Addr Description (Hex) F00 F01 F02 F03 F04 FFF 60 Zarlink Semiconductor Inc ...

Page 61

... Bit [2]: Control Frame 2 interrupt. Control Frame receive buffer2 has data for CPU to read Bits [6:3]: Reserved Bit [7]: Device Timeout Detected interrupt Note: This bit is not self-cleared. After reading, the CPU has to clear the bit writing 0 to it. ZL50400 61 Zarlink Semiconductor Inc. Data Sheet ...

Page 62

... ECR1Pn[2:0] for configuration). Hardware will still poll PHY for link status Force Link Down Disable the port. Hardware does not talk to PHY Force Link Up The configuration in ECR1Pn[2:0] is used for (speed/duplex/flow control) setup. Hardware does not talk to PHY. ZL50400 62 Zarlink Semiconductor Inc. Data Sheet ...

Page 63

... Enable Asymmetric flow control When this bit is set and flow control is on (bit [0] = 0), the device does not send out flow control frames, but it’s receiver interprets and processes flow control frames. ZL50400 Frame is dropped Frame is dropped Frame is dropped. Source MAC address is learned. ...

Page 64

... Rate control timer select (RMAC ports only microsecond refreshing time (Default millisecond refreshing time Bit [4] 0 Bit [5] Reserved. Must be 0. ZL50400 Frame is dropped Frame is dropped Frame is dropped. Source MAC address is learned. Frame is forwarded. Source MAC address is learned. (Default) 64 Zarlink Semiconductor Inc. ...

Page 65

... Bits [7:6] Security Enable. The ZL50400 checks the incoming data for one of the following conditions: • If the source MAC address of the incoming packet is in the MAC table and is defined as secure address but the ingress port is not the same as the port associated with the MAC address in the MAC table. ...

Page 66

... MCT and associated with the originating source port. The frame loopback will only work for unicast packets. Bit [6]: Link Heart Beat Receive 0: Disable (Default). Also clears all MAC LHB status. 1: Enable Bit [7]: Soft reset. 0: Normal operation (Default) 1: Reset. Not self clearing. ZL50400 66 Zarlink Semiconductor Inc. Data Sheet ...

Page 67

... In this mode, the packet is looped back in the MAC layer before going out of the chip. You must force linkup at full duplex as well. External loopback is another level of system diagnostic which involves the PHY device to loopback the packet. Bits [4:3]: Interface mode MII mode (Default) ZL50400 67 Zarlink Semiconductor Inc. Data Sheet ...

Page 68

... VLANType_LOW: Lower 8 bits of the VLAN type code (Default 0x00) 12.3.2.2 AVTCH – VLAN Type Code Register High I²C Address 029; CPU Address:h101 Accessed by CPU and I²C (R/W) Bits [7:0]: VLANType_HIGH: Upper 8 bits of the VLAN type code (Default is 0x81) ZL50400 68 Zarlink Semiconductor Inc. Data Sheet ...

Page 69

... PVMAP02_0,1,3 I²C Address h2C,36,40; CPU Address:h10A, 10B, 10D (Port 2) PVMAP03_0,1,3 I²C Address h2D,37,41; CPU Address:h10E, 10F, 111 (Port 3) PVMAP04_0,1,3 I²C Address h2E,38,42; CPU Address:h112, 113, 115 (Port 4) PVMAP05_0,1,3 I²C Address h2F,39,43; CPU Address:h116, 117, 119 (Port 5) ZL50400 69 Zarlink Semiconductor Inc. Data Sheet ...

Page 70

... Enable - When Well Known or User Define logical port force discard enabled, force any IP packet with logical port number matching logical port numbers to CPU. 12.3.3 (Group 2 Address) Port Trunking Groups Trunk Group – eight RMAC ports can be selected for each trunk group. ZL50400 70 Zarlink Semiconductor Inc. Data Sheet ...

Page 71

... Hash result 3 destination port number (Default 0) 12.3.3.4 TRUNKn_HASH54 – Trunk group n hash result 5/4 destination port number CPU Address:h20A+ trunk group) Accessed by CPU (R/W) Bits [3:0] Hash result 4 destination port number (Default 0) Bits [7:4] Hash result 5 destination port number (Default 0) ZL50400 TRUNK0 ...

Page 72

... Port 7-0 bit map for multicast hash. (Default 0xFF) 12.3.3.7 MULTICAST_HASHn-1 – Multicast hash result 0~7 mask byte 1 CPU Address:h229+ hash value) Accessed by CPU (R/W) Bits [1:0]: Port 9-8 bit map for multicast hash. (Default 0x3) Bit [2]: Reserved (Default 0x1) ZL50400 HASH0-1 HASH0-0 HASH1-1 HASH1-0 HASH2-1 HASH2-0 HASH3-1 HASH3-0 ...

Page 73

... CPU Address:h301 Accessed by CPU (R/W) Bits [7:0]: Byte 1 (bits [15:8]) of the CPU MAC address (Default 0) 12.3.4.3 MAC2 – CPU MAC address byte 2 CPU Address:h302 Accessed by CPU (R/W) Bits [7:0]: Byte 2 (bits [23:16]) of the CPU MAC address (Default 0) ZL50400 MAC3 MAC2 MAC1 MAC0 73 Zarlink Semiconductor Inc. Data Sheet 0 (MC bit) ...

Page 74

... Device Timeout Detected interrupt 12.3.4.8 INTP_MASK0 – Interrupt Mask for MAC Port 0,1 CPU Address:h310 Accessed by CPU (R/W) The CPU can dynamically mask the interrupt when it is busy and doesn’t want to be interrupted (Default 0x00 Mask the interrupt ZL50400 74 Zarlink Semiconductor Inc. Data Sheet ...

Page 75

... Bit [3]: Select Queue 3 Bit [4]: Select Multicast Queue 0 Bit [5]: Select Multicast Queue 1 Bit [6]: Select Multicast Queue 2 Bit [7]: Select Multicast Queue 3 Note: Strict priority applies between different selected queues (UQ3>UQ2>UQ1>UQ0>MQ3>MQ2>MQ1>MQ0). ZL50400 75 Zarlink Semiconductor Inc. Data Sheet ...

Page 76

... Reserved Bits [6:4]: Bits [42:40] of Port 3 CPU MAC address Bit [7]: Reserved 12.3.4.14 MAC45 – Increment MAC port 4,5 address CPU Address:h327 Accessed by CPU (RW) Bits [2:0]: Bits [42:40] of Port 4 CPU MAC address Bit [3]: Reserved Bits [6:4]: Bits [42:40] of Port 5 CPU MAC address Bit [7]: Reserved ZL50400 76 Zarlink Semiconductor Inc. Data Sheet ...

Page 77

... Number of granules for the frame Bits [35:21] Tail pointer Bits [50:36] Header Pointer Bit [51] Multicast frame (has to be one if more than one destination port) Bits [54:52] Reserved Bit [55] Command valid (will be processed on the rising edge of the signal) ZL50400 CQ4 CQ3 CQ2 77 Zarlink Semiconductor Inc. Data Sheet 0 CQ1 CQ0 ...

Page 78

... Bit [15]: 12.3.4.20 CPURLSINFO0 - CPURLSINFO4 – Receive Queue Status CPU Address:h33A-33E Accessed by CPU, (R/W) CR4 CPU Queue insertion command Header pointer Bits [14:0]: Tail pointer Bits [30:15] Number of granules for the release Bits [38:32] ZL50400 15 0 CG1 CG0 CR3 CR2 CR1 CR0 78 Zarlink Semiconductor Inc. Data Sheet 0 ...

Page 79

... AGETIME_LOW – MAC address aging time Low I²C Address h049; CPU Address:h400 Accessed by CPU and I²C (R/W) Used in conjuction with AGETIME_HIGH. The ZL50400 removes the MAC address from the data base and sends a Delete MAC Address Control Command to the CPU. Bits [7:0]: Low byte of the MAC address aging timer (Default 0x5C) 12 ...

Page 80

... Use TOS [4:2] bits to map the transmit priority (Default) 1 – Use TOS [7:5] bits to map the transmit priority Bit [7]: Select TOS bits for Drop priority 0 – Use TOS [4:2] bits to map the drop priority (Default) 1 – Use TOS [7:5] bits to map the drop priority ZL50400 80 Zarlink Semiconductor Inc. Data Sheet ...

Page 81

... I²C Address 090, CPU Address 513 2 Accessed by CPU and I C (R/W) Bits [3:0]: Corresponds to the frame drop percentage Y% for WRED. Granularity 6.25%. Bits [7:4]: Corresponds to the frame drop percentage X% for WRED. Granularity 6.25%. See Programming QoS Registers application note, ZLAN-42, for more information ZL50400 81 Zarlink Semiconductor Inc. Data Sheet ...

Page 82

... Class 1 FCB Reservation Buffer reservation for class 1. Granularity 16 granules. (Default 0) 12.3.6.10 C2RS – Class 2 Reserve Size I²C Address h076, CPU Address 51A Accessed by CPU and I²C (R/W) Bits [7:0]: Class 2 FCB Reservation Buffer reservation for class 2. Granularity 16 granules. (Default 0) ZL50400 82 Zarlink Semiconductor Inc. Data Sheet ...

Page 83

... VLAN priority field. For example, programming a value of 7 into bit 2:0 of the AVPML register would map packet VLAN priority 0 into Internal transmit priority 7. The new priority is used inside the ZL50400. When the packet goes out it carries the original priority. Bits [2:0]: ...

Page 84

... Map TOS field in IP packet into eight level transmit priorities Bit [0]: Priority when the TOS field is 2 (Default 0) Bits [3:1]: Priority when the TOS field is 3 (Default 0) Bits [6:4]: Priority when the TOS field is 4 (Default 0) Bit [7]: Priority when the TOS field is 5 (Default 0) ZL50400 84 Zarlink Semiconductor Inc. Data Sheet ...

Page 85

... Frame drop priority when TOS field is 7 (Default 0) 12.3.6.20 USER_PROTOCOL_n – User Define Protocol 0~7 I²C Address h0B3+n, CPU Address:h550+n Accessed by CPU and I²C (R/W) (Default 00) This register is duplicated eight times from PROTOCOL 0~7 and allows the CPU to define eight separate protocols. Bits [7:0]: User Define Protocol ZL50400 85 Zarlink Semiconductor Inc. Data Sheet ...

Page 86

... Enable Protocol 7 Force Discard User Defined Logical Ports and Well Known Ports The ZL50400 supports classifying packet priority through layer 4 logical port information. It can be setup by 8 Well Known Ports, 8 User Defined Logical Ports, and 1 User Defined Range. The 8 Well Known Ports supported are: • ...

Page 87

... WELL_KNOWN_PORT[7:6]_PRIORITY- Well Known Logic Port 7 and 6 Priority I²C Address h0AB, CPU Address 563 Accessed by CPU and I²C (R/W) Bits [3:0]: Priority setting, transmission + dropping, for Well known port 6 (22 for ssh) Bits [7:4]: Priority setting, transmission + dropping, for Well known port 7 (554 for rtsp) ZL50400 87 Zarlink Semiconductor Inc. Data Sheet ...

Page 88

... Bit [3]: Enable Well Known Port 3 Force Discard Bit [4]: Enable Well Known Port 4 Force Discard Bit [5]: Enable Well Known Port 5 Force Discard Bit [6]: Enable Well Known Port 6 Force Discard Bit [7]: Enable Well Known Port 7 Force Discard ZL50400 88 Zarlink Semiconductor Inc. Data Sheet ...

Page 89

... USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority I²C Address h0A4, CPU Address 592 Accessed by CPU and I²C (R/W) Bits [3:0]: Priority setting, transmission + dropping, for logic port 4 Bits [7:4]: Priority setting, transmission + dropping, for logic port 5 (Default 00) ZL50400 7 TCP/UDP Logic Port Low 7 TCP/UDP Logic Port High 89 Zarlink Semiconductor Inc. ...

Page 90

... Enable User Port 2 Force Discard Bit [3]: Enable User Port 3 Force Discard Bit [4]: Enable User Port 4 Force Discard Bit [5]: Enable User Port 5 Force Discard Bit [6]: Enable User Port 6 Force Discard Bit [7]: Enable User Port 7 Force Discard ZL50400 90 Zarlink Semiconductor Inc. Data Sheet ...

Page 91

... RLOW and RHIGH form a range for logical ports to be classified with priority specified in RPRIORITY. Bit [0]: Drop Priority (inclusive only) Bits [3:1] Transmit Priority (inclusive only) Bits [5:4] Reserved Bits [7: Filtering 01 - Exclusive Filtering (x<=RLOW or x>=RHIGH Inclusive Filtering (RLOW<x<RHIGH Invalid ZL50400 91 Zarlink Semiconductor Inc. Data Sheet ...

Page 92

... Accessed by CPU and I²C (R/W) Bit [0]: Statistic Counter 0 – Disable (Default) 1 – Enable (all ports) When statistic counter is enable, an interrupt control frame is generated to the CPU, every time a counter wraps around. This feature requires an external CPU. Bit [1]: 0 ZL50400 92 Zarlink Semiconductor Inc. Data Sheet ...

Page 93

... Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY, and no VALID; then program MII command. 12.3.7.5 MIIC1 – MII Command Register 1 CPU Address:h604 Accessed by CPU (R/W) Bits [7:0]: MII Command Data [15:8] Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command. ZL50400 93 Zarlink Semiconductor Inc. Data Sheet ...

Page 94

... MII command. Writing this register will initiate a serial management cycle to the MII management interface. 12.3.7.8 MIID0 – MII Data Register 0 CPU Address:h607 Accessed by CPU (RO) Bits [7:0]: MII Data [7:0] 12.3.7.9 MIID1 – MII Data Register 1 CPU Address:h608 Accessed by CPU (RO) Bits [7:0]: MII Data [15:8] ZL50400 94 Zarlink Semiconductor Inc. Data Sheet ...

Page 95

... The checksum formula is I²C register = When the ZL50400 boots from the EEPROM the checksum is calculated and the value must be zero. If the checksum is not zeroed the ZL50400 does not start and pin CHECKSUM_OK is set to zero. ZL50400 95 Zarlink Semiconductor Inc. Data Sheet ...

Page 96

... I²C Address 0C0, CPU Address:h621 Accessed by CPU and I²C (R/W) Bits [7:0] FCB Base address bit 15:8 (Default 0x60) 12.3.7.18 FCB Base Address Register 2 I²C Address 0C1, CPU Address:h622 Accessed by CPU and I²C (R/W) Bits [7:0] FCB Base address bit 23:16 (Default 0) ZL50400 96 Zarlink Semiconductor Inc. Data Sheet ...

Page 97

... RMAC_MIRROR0 – RMAC Mirror 0 CPU Address 710 Accessed by CPU (R/W) Bits [2:0]: Source port to be mirrored Bit [3]: Mirror path 0: Receive 1: Transmit Bits [6:4]: Destination port for mirrored traffic Bit [7]: Mirror enable ZL50400 DEST_MAC3 DEST_MAC2 DEST_MAC1 [31:24] [23:16] [15:8] (Default 00) (Default 00) (Default 00) SRC_MAC3 SRC_MAC2 SRC_MAC1 [31:24] [23:16] [15:8] ...

Page 98

... Once the packet rate is reached, packets will be dropped. To turn off the rate limit, program the field to 0. Time base is based on register FCR0 [6:4] Bits [3:0]: Multicast Rate Control. Number of multicast packets allowed within the time defined in bits the Flooding Control Register (FCRn). (Default 0). ZL50400 98 Zarlink Semiconductor Inc. Data Sheet ...

Page 99

... Expressed in multiples of 16 granules. More than this number used on a source port will trigger either random drop or flow control (Default 0x12) 12.3.9.9 QOSC00, QOSC01 - Classes Byte Limit port 0 Accessed by CPU and I²C (R/W) • QOSC00 – BYTE_L1 (I²C Address h078, CPU Address 880) • QOSC01 – BYTE_L2 (I²C Address h079, CPU Address 881) ZL50400 99 Zarlink Semiconductor Inc. Data Sheet ...

Page 100

... W0. Default scheduling method will be strict priority across all queues. Only when the bit 7 in the class is set, the queue will be scheduled as WFQ. The credit number also works as shaper credit if bit 6 is set. The queue with ZL50400 2 C Address h088, CPU Address 890) ...

Page 101

... Accessed by CPU (R/W) Test group selection for testout[15:8]. 12.3.10.3 TESTOUT0, TESTOUT1 – Testmux Output [7:0], [15:8] CPU Address E02, E03 Accessed by CPU (RO) 12.3.10.4 MASK0-MASK4 – Timeout Reset Mask CPU Address E10-E14 Accessed by CPU (R/W) Disable timeout reset on selected state machine status. ZL50400 101 Zarlink Semiconductor Inc. Data Sheet ...

Page 102

... Bit [1]: RX SFD detection NOT idle for 5 sec Bit [2]: RXINF NOT idle for 5 sec Bit [3]: PTCTL NOT idle for 5 sec Bit [4]: Reserved Bit [5]: LHB frame detected Bit [6] LHB receiving timeout Bit [7]: ZL50400 23 15 BT2 BT1 102 Zarlink Semiconductor Inc. Data Sheet 0 BT0 ...

Page 103

... L1 WRED level Bit [9]: priority queue 3 reach L2 WRED level Bit [10]: priority 0 MC queue full Bit [11]: priority 1 MC queue full Bit [12]: priority 2 MC queue full Bit [13]: Priority 3 MC queue full Bits [15:14]: Reserved ZL50400 PQSTB PQSTA 103 Zarlink Semiconductor Inc. Data Sheet 0 ...

Page 104

... Priority queue 3 reach L1 WRED level Bit [9]: Priority queue 3 reach L2 WRED level Bit [10]: Priority 0 MC queue full Bit [11]: Priority 1 MC queue full Bit [12]: Priority 2 MC queue full Bit [13]: Priority 3 MC queue full Bits [15:14]: Reserved ZL50400 15 PQSTB PQSTA 104 Zarlink Semiconductor Inc. Data Sheet 0 ...

Page 105

... CPU Address EB0+n Accessed by CPU (R/W) Bit [0]: Suspend port scheduling (no departure) Bit [1]: Reset queue Bits [4:2]: Reserved Bit [5]: Force out MAC control frame Bit [6]: Force out XOFF flow control frame Bit [7]: Force out XON flow control frame ZL50400 105 Zarlink Semiconductor Inc. Data Sheet ...

Page 106

... BMBISTR0, BMBISTR1 CPU Address EBB, EBC Accessed by CPU (RO) 12.3.10.15 BMControl CPU Address EBD Accessed by CPU (R/W) Bits [3:0]: Block Memory redundancy control 0: Use hardware detected value All others: Overwrite the hardware detected memory swap map Bits [7:4]: Reserved ZL50400 106 Zarlink Semiconductor Inc. Data Sheet ...

Page 107

... Bits [7:0] CPU address EC2 Accessed by CPU (R/W) Fcb_head_ptr[14:8]. The head pointer of free granule link that CPU assigns. Bits [6:0] Set 1 to write Bit [7] If CPU wants to write again, CPU has to clear bit 15 and then set bit 15. ZL50400 107 Zarlink Semiconductor Inc. Data Sheet ...

Page 108

... The information of BM release FIFO is relocated to registers BM_RLSFF_INFO (address ECD, ECC, ECB, ECA, EC9 and EC8). If the FIFO is not empty, CPU can read out the next by setting the bit 0. Read only happens when bit 0 is changing from ZL50400 108 Zarlink Semiconductor Inc. ...

Page 109

... Accessed by CPU (RO) Bits [4:0] Rls_count[6:2] Bit [ then It is multicast packet. Bits [7:6] Rls_src_port[1:0[ CPU address ECD Accessed by CPU (RO) Bits [1:0] Rls_src_port[3:2] Bits [3:2] Class[1:0] Bit [4] This release request is from QM directly. Bits [7:5] Entries count in release FIFO, 0 means FIFO is empty ZL50400 109 Zarlink Semiconductor Inc. Data Sheet ...

Page 110

... Busy reading configuration from I²C 0: Not busy (not reading configuration from I²C) Bit [2]: 1: BIST in progress 0: BIST not running Bit [3]: 1: RAM Error 0: RAM OK Bits [5:4]: Device Signature 10: ZL50400 device Bits [7:6]: Revision 00: Initial Silicon 01: Second Silicon ZL50400 110 Zarlink Semiconductor Inc. Data Sheet ...

Page 111

... This register provides various internal information as selected in DPST bit [4:0]. Refer to the PHY Port Control Application Note, ZLAN-37. Bit [0] Flow control enable 1: Flow control 0: No flow control Bit [1] Full duplex port 1: Full duplex 0: Half duplex Bit [2] Fast Ethernet port 1: FE Port Bit [3] Link is down 1: Link down 0: Link up ZL50400 111 Zarlink Semiconductor Inc. Data Sheet ...

Page 112

... Caution: Stress above those listed may damage the device. Exposure to the Absolute Maximum Ratings for extended periods may affect device reliability. Functionality at or above these limits is not implied. 13.2 DC Electrical Characteristics V = 3.3 V +/- 10 1.8 V +/- 5% DD ZL50400 -65GC to +150GC -40GC to +85GC +125GC +2. +3. +1. + ...

Page 113

... Output Capacitance OUT C I/O Capacitance I/O 6 Thermal resistance with 0 air flow ja 6 Thermal resistance with 1 m/s air flow ja Thermal resistance with 2 m/s air flow 6 ja Thermal resistance between junction and case 6 jc ZL50400 Min. 2.4 2.0 < < OUT CC 113 Zarlink Semiconductor Inc. Data Sheet Typ. Max. ...

Page 114

... R1 Bootstrap Pins Outputs Figure 10 - Typical Reset & Bootstrap Timing Diagram Symbol Parameter R1 Delay until RESETOUT# is tri-stated R2 Bootstrap stabilization R3 RESETOUT# assertion ZL50400 Tri-Stated R3 Inputs R2 Min. Typ RESETOUT# state is then determined by the external pull-up/down resistor Bootstrap pins sampled on rising edge of ...

Page 115

... Figure Characteristics – Reduced Media Independent Interface (RX) Symbol M2 M[7:0]_RXD[1:0] Input Setup Time M3 M[7:0]_RXD[1:0] Input Hold Time M4 M[7:0]_CRS_DV Input Setup Time M5 M[7:0]_CRS_DV Input Hold Time M6 M[7:0]_TXEN Output Delay Time M7 M[7:0]_TXD[1:0] Output Delay Time ZL50400 M_CLK M6-max M6-min Mn_TXEN M7-max M7-min Mn_TXD[1:0] M_CLK M2 Mn_RXD M3 M4 Mn_CRS_DV ...

Page 116

... MM2 M[9,7:0]_RXD[3:0] Input Setup Time MM3 Mn_RXD[3:0] Input Hold Time MM4 M[9,7:0]_CRS_DV Input Setup Time MM5 Mn_CRS_DV Input Hold Time MM6 Mn_TXEN Output Delay Time MM7 Mn_TXD[3:0] Output Delay Time ZL50400 Mn_TXCLK MM6-max MM6-min Mn_TXEN MM7-max MM7-min Mn _TXD[3:0] Mn_RXCLK MM2 Mn_RXD[3:0] MM ...

Page 117

... M[7:0]_RXD Input Setup Time SM3 M[7:0]_RXD Input Hold Time SM4 M[7:0]_CRS_DV Input Setup Time SM5 M[7:0]_CRS_DV Input Hold Time SM6 M[7:0]_TXEN Output Delay Time SM7 M[7:0]_TXD Output Delay Time ZL50400 Mn_ TXCLK SM6-max SM6-min Mn_TXEN SM7-max SM7-min Mn_TXD Mn_RXCLK SM2 Mn_RXD ...

Page 118

... MDIO Input Setup and Hold Timing Figure 17 - MDIO Input Setup and Hold Timing Symbol D1 MDIO input setup time D2 MDIO input hold time D3 MDIO output delay time ZL50400 MDC D1 D2 MDIO MDC D3-max D3-min MDIO Figure 18 - MDIO Output Delay Timing MDC=500 KHz Parameter Min ...

Page 119

... I²C Input Setup Timing Symbol S1 SDA input setup time S2 SDA input hold time S3* SDA output delay time * Open Drain Output. Low to High transistor is controlled by external pullup resistor. ZL50400 SCL S1 SDA Figure 19 - I²C Input Setup Timing SCL S3-max S3-min SDA Figure 20 - I²C Output Delay Timing Parameter Min ...

Page 120

... STROBE Dataout Figure 22 - Serial Interface Output Delay Timing Symbol D1 DATAIN setup time D2 DATAIN hold time D3 DATAOUT output delay time D4 STROBE low time D5 STROBE high time ZL50400 Figure 21 - Serial Interface Setup Timing D3-max D3-min Parameter Min. (ns ...

Page 121

... Symbol Parameter TCK frequency of operation TCK cycle time TCK clock pulse width TRST# assert time J1 TMS, TDI data setup time J2 TMS, TDI data hold time J3 TCK to TDO data valid ZL50400 J1 J2 Figure 23 - JTAG Timing Diagram Min. Typ. Max ...

Page 122

... Clarified that only bit [7] is not self-clearing 14.5 November 2004 • Added section “Default Switch Configuration and Initialization Sequence” on page 20 • Removed reference to direct register INDEX_REG1 (address 0x1) from SSI diagrams, as not applicable ZL50400 122 Zarlink Semiconductor Inc. Data Sheet ...

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... TOP VIEW SIDE VIEW c Zarlink Semiconductor 2002 All rights reserved. 1 ISSUE 213730 ACN 14Nov02 DATE APPRD. BOTTOM VIEW b Previous package codes Dimension MIN MAX 1. 0.30 0.50 0.53 REF A2 D 16.90 17.10 E 16.90 17.10 b 0.40 0.60 e 1.00 N 208 Conforms to JEDEC MO-192 Package Code ...

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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...