zl50400 Zarlink Semiconductor, zl50400 Datasheet - Page 92

• Manufacturer Part Number: zl50400
• Description: Lightly Managed/unmanaged 9-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

12.3.7
12.3.7.1
I²C Address 0BC, CPU Address:h600
Accessed by CPU and I²C (R/W)
12.3.7.2
I²C Address 0BD, CPU Address:h601
Accessed by CPU and I²C (R/W)
12.3.7.3
I²C Address 0BE, CPU Address:h602)
Accessed by CPU and I²C (R/W)
(Group 6 Address) MISC Group
Bits [4:0]:
Bits [5]
Bits [6]
Bit [7]:
Bits [3:0]:
Bits [7:4]:
Bit [0]:
Bit [1]:
MII_OP0 – MII Register Option 0
MII_OP1 – MII Register Option 1
FEN – Feature Register
Vendor specified link status register address (null value means don’t use it)
(Default 00). This is used if the Linkup bit position in the PHY is non-standard
Disable jabber detection. This is for HomePNA applications or any serial
operation slower than 10 Mbps.
0 = Enable
1 = Disable
Reserved
Half duplex flow control feature
0 = Half duplex flow control always enable
1 = Half duplex flow control by negotiation
Duplex bit location in vendor specified register
Speed bit location in vendor specified register
(Default 00)
Statistic Counter
0 – Disable (Default)
1 – Enable (all ports)
When statistic counter is enable, an interrupt control frame is generated to
the CPU, every time a counter wraps around. This feature requires an
external CPU.
0
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ZL50400
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Data Sheet