zl50400 Zarlink Semiconductor, zl50400 Datasheet - Page 93

• Manufacturer Part Number: zl50400
• Description: Lightly Managed/unmanaged 9-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

12.3.7.4
CPU Address:h603
Accessed by CPU (R/W)
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY, and no VALID; then
program MII command.
12.3.7.5
CPU Address:h604
Accessed by CPU (R/W)
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command.
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Bits [7:0]:
Bits [7:0]:
MIIC0 – MII Command Register 0
MIIC1 – MII Command Register 1
Support DS EF Code.
0 – Disable (Default)
1 – Enable (all ports)
When 101110 is detected in DS field (TOS[7:2]), the frame priority is set for
110 and drop is set for 0.
Reserved. Must be 0.
Reserved. Must be 1.
Report to CPU
0 – Disable (Default)
1 – Enable
When disable new MAC address report or aging reports are disable for all
ports. When enable, register SE_OPMODE is used to enable/disable
selectively each function.
MII Management State Machine
0: Enable (Default)
1: Disable
This bit must be set so that there is no contention on the MDIO bus between
MII Management state machine and MIIC & MIID PHY register accesses.
MCT Link List structure
0 – Enable (Default)
1 – Disable
MII Command Data [7:0]
MII Command Data [15:8]
Zarlink Semiconductor Inc.
ZL50400
93
Data Sheet