zl50400 Zarlink Semiconductor, zl50400 Datasheet - Page 39

• Manufacturer Part Number: zl50400
• Description: Lightly Managed/unmanaged 9-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

Also, when shaping is enabled, it is possible for a queue to explode in length if fed by a greedy source. The reason
is that a shaper is by definition not work-conserving; that is, it may hold back from sending a packet even if the line
is idle. Though we do have global resource management, we do nothing other than per port WRED to prevent this
situation locally. We assume the traffic is policed at a prior stage to the ZL50400 or WRED dropping is fine and shall
restrain this situation.
7.5
The ZL50400 provides a rate control function on its RMAC ports. The concept is much the same as shaping, except
that it applies to both ingress and egress directions and the control is per port rather than per queue. It provides a
way of reducing the total bandwidth of all frames received from or transmitted to a port, to a rate below wire speed.
As with shaping, the maximum burst size can also be configured.
Rate control may be a valuable feature on RMAC ports in access applications where the service provider would like
to limit the traffic received and transmitted by each port independently of each other, and independently of the
physical line rate. The service provider can then provide differential pricing, based on the negotiated bandwidth
requirements for each user. In such applications of the ZL50400, the MMAC port is viewed as an uplink port, where
rate control is not desired.
See Rate Control application note, ZLAN-33, for more information.
7.6
Because the number of FDB slots is a scarce resource, and because we want to ensure that one misbehaving
source port or class cannot harm the performance of a well-behaved source port or class, we introduce the concept
of buffer management into the ZL50400. Our buffer management scheme is designed to divide the total buffer
space into numerous reserved regions and one shared pool, as shown in Figure 8 on page 40.
As shown in the figure, the FDB pool is divided into several parts. A reserved region for temporary frames stores
frames prior to receiving a switch response. Such a temporary region is necessary, because when the frame first
enters the ZL50400, its destination port and class are as yet unknown, and so the decision to drop or not needs to
be temporarily postponed. This ensures that every frame can be received first before subjecting them to the frame
drop discipline after classifying.
Three priority sections, one for each pair of the first six priority classes, ensure a programmable number of FDB
slots per class. The lowest two classes do not receive any buffer reservation. Furthermore, a frame is stored in the
region of the FDB corresponding to its class. As we have indicated, the eight classes use only two transmission
scheduling queues for RMAC ports (four queues for the MMAC & CPU ports), but as far as buffer usage is
concerned, there are still eight distinguishable classes.
Another segment of the FDB reserves space for each of the 10 ports — 9 ports for Ethernet and one CPU port (port
number 8). Each port has it’s own programmable source port reservation. These 10 reserved regions make sure
that no well-behaved source port can be blocked by another misbehaving source port.
In addition, there is a shared pool, which can store any type of frame. The frame engine allocates the frames first in
the three priority sections. When the priority section is full or the packet has priority 1 or 0, the frame is allocated in
the shared pool. Once the shared pool is full the frames are allocated in the section reserved for the source port.
The following registers define the size of each section of the Frame data Buffer:
-
-
-
-
-
-
-
Rate Control
Buffer Management
PR100_N - Port Reservation for RMAC Ports
PR100_CPU - Port Reservation for CPU Port
PRM - Port Reservation for MMAC Port
SFCB - Share FCB Size
C1RS - Class 1 Reserve Size (priority 2 & 3)
C2RS - Class 2 Reserve Size (priority 4 & 5)
C3RS - Class 3 Reserve Size (priority 6 & 7)
Zarlink Semiconductor Inc.
ZL50400
39
Data Sheet