zl50400 Zarlink Semiconductor, zl50400 Datasheet - Page 20

• Manufacturer Part Number: zl50400
• Description: Lightly Managed/unmanaged 9-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

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1.6
The ZL50400 will come out of reset in a default configuration, which will allow for basic L2 switching and automatic
MAC address learning.
In unmanaged mode, the default configuration will take effect immediately after reset. The default settings can be
changed using the optional EEPROM.
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System Defaults
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Per-port Defaults
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Module Detect bootstrap, TSTOUT[9], should be pulled-down
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Power Saving bootstrap, TSTOUT[11], should be normally pulled-up
Timeout Reset bootstrap, TSTOUT[12], should be pull-down
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Default Switch Configuration and Initialization Sequence
Port-based VLAN
MAC address 00-00-00-00-00-00 not learned
Drop MAC addresses 01-80-C2-00-00-01~F
No IP Multicast switching support
Trunking and mirroring disabled
MAC address agetime is 300 seconds
VLAN 802.1p prioritization
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96 queued unicast/multicast frames will trigger flow control
All WRED drop percentages equal to 0%
Unicast/multicast/broadcast flood control disabled
No shared or per-class buffer pools
Disable per-port fixed priority and drop precedence
Disable asynchronous flow control
Spanning Tree per-port state equal to forwarding
Don’t filter tagged/untagged VLAN frames
Automatic learning enabled
Per-port security disabled
Support frame size 64 <= n <= 1522
Pad transmit frames < 64B
Standard preamble
Strict Priority scheduling
FE Ports
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CPU Interface bootstrap, TSTOUT[3], should be pulled-up to indicate unmanaged SSI CPU interface.
To enable lightly managed mode, pulled-downSSI Device ID bootstrap, TSTOUT[6:4], should be
pulled-down to indicate device ID 0x0 for the SSI interface. Can be changed to whatever device ID
required if more than one device on the SSI bus.
EEPROM bootstrap, TSTOUT[7], should be pulled-up to disable until the system is debugged. You
can pull-down this bootstrap if using the optional EEPROM in unmanaged mode (NOTE: this bootstrap
is not valid in any other CPU mode)
In lightly managed mode, you can enable the optional Module Detect feature
If enabled, need to use Mn_TXEN to indicate module type
Once system is debugged, you can enable the optional feature with pull-up (Refer to section 2.7 for
more details on this feature)
All priority bits mapped to priority 0 (lowest)
RMII mode
Auto-negotiate 100 M/Full Duplex/Flow Control
Rate control disabled
per-source port buffer pool of 96 buffers, with flow control threshold of 48 buffers
Zarlink Semiconductor Inc.
ZL50400
20
Data Sheet