zl50400 Zarlink Semiconductor, zl50400 Datasheet - Page 61

• Manufacturer Part Number: zl50400
• Description: Lightly Managed/unmanaged 9-port 10/100 M Ethernet Switch
• Manufacturer: Zarlink Semiconductor

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12.2.5
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Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bits [7:6]:
Bit [0]:
Bit [1]:
Bit [2]:
Bits [6:3]:
Bit [7]:
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bits [7:6]:
When the CPU reads this register:
Interrupt sources (8 bits)
Address = 5 (read/write)
Interrupt Register
is self-cleared.
Set Control Frame Transmit buffer1 ready, after CPU reads out a complete frame from the buffer.
This bit is self-cleared.
Set Control Frame Transmit buffer2 ready, after CPU reads out a complete frame from the buffer.
This bit is self-cleared.
Set this bit to indicate CPU received a whole frame (transmit FIFO frame receive done), and
flushed the rest of frame fragment, If occurs. This bit will be self-cleared.
will be self-cleared.
can be used for software debug. For normal operation must be '0'.
Reserved. Must be '0'
Set Control Frame Receive buffer ready, after CPU writes a complete frame into the buffer. This bit
Set this bit to indicate that the following Write to the Receive FIFO is the last one (EOF). This bit
Set this bit to re-start the data that is sent from the CPU to Receive FIFO (re-align). This feature
Control Frame receive buffer ready, CPU can write a new frame
1 – CPU can write a new control command 1
0 – CPU has to wait until this bit is 1 to write a new control command 1
Control Frame transmit buffer1 ready for CPU to read
1 – CPU can read a new control command 1
0 – CPU has to wait until this bit is 1 to read a new control command
Control Frame transmit buffer2 ready for CPU to read
1 – CPU can read a new control command 1
0 – CPU has to wait until this bit is 1 to read a new control command
Transmit FIFO has data for CPU to read (TXFIFO_RDY)
Receive FIFO has space for incoming CPU frame (RXFIFO_SPOK)
Transmit FIFO End Of Frame (TXFIFO_EOF)
Reserved
CPU frame interrupt
Control Frame 1 interrupt. Control Frame receive buffer1 has data for CPU to read
Control Frame 2 interrupt. Control Frame receive buffer2 has data for CPU to read
Reserved
Device Timeout Detected interrupt
Note: This bit is not self-cleared. After reading, the CPU has to clear the bit writing 0 to it.
Zarlink Semiconductor Inc.
ZL50400
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Data Sheet