tmp89fm42a TOSHIBA Semiconductor CORPORATION, tmp89fm42a Datasheet - Page 40

• Manufacturer Part Number: tmp89fm42a
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA000
Table 2-2 Steps for Switching the High-Frequency Reference Clock (fh) from fosc to fc
Note:Be sure to follow the above steps when switching the high-frequency reference clock.
Internal high-frequency
clock (fosc)
External high-frequency
clock (fc)
SYSCR1<OSCSEL>
High-frequency
reference clock (fh)
Step
1
2
3
4
5
Figure 2-5 Switching the High-Frequency Reference Clock (fh) (fosc→fc)
P0FC0
0
1
1
1
1
Note 1: When the high-frequency reference clock (fh) is switched, the hardware synchronizes the external
Note 2: After changing SYSCR1<OSCSEL>, be sure to wait for at least 2 machine cycles before clearing
Note 3: SYSCR1<OSCSEL> must be set while SYSCR2<SYSCK> = "0" (during the NORMAL1 or NOR-
Note 4: Setting SYSCR2<XEN> to "1" while P0FC0 = "0" generates a system clock reset.
Note 5: If SYSCR2<XEN> is set to "1" while SYSCR2<XEN> = "1", the warm-up counter does not start
・ Switching from fosc to fc
<OSCEN>
the external high-frequency clock (fc).
by using the warm-up counter, set SYSCR1<OSCSEL> to "1".
reference clock (fh) changes to the external high-frequency clock (fc).
clear SYSCR2<OSCEN> to "0" to stop the internal high-frequency clock (fosc). If
SYSCR2<OSCEN> is cleared to "0" while the reference clock (fh) is being switched, a system
clock reset is generated.
SYSCR2
high-frequency clock (fc) and the internal high-frequency clock (fosc). While this is done, fh stops
for a maximum of 2.5/fc [s].
SYSCR2<OSCEN> to "0". If SYSCR2<OSCEN> is cleared to "0" without waiting for at least 2
machine cycles, a system clock reset is generated.
MAL2 mode). Writing to SYSCR1<OSCSEL> while SYSCR2<SYSCK> = "1" (during the SLOW1
or SLOW2 mode) has no effect.
counting the source clock.
With the relevant bits in the P0FC0 register set to "1", set SYSCR2<XEN> to "1" to enable
After making sure that the external high-frequency clock (fc) has achieved stable oscillation
A maximum of 2/fosc + 2.5/fc [s] after SYSCR1<OSCSEL> is set to "1", the high-frequency
After the reference clock (fh) has been switched, wait for at least 2 machine cycles, and then
1
1
1
1
0
SYSCR2
<XEN>
0
0
1
1
1
<OSCSEL>
SYSCR1
0
0
0
1
1
Page 21
Main system
fosc→fc
clock
fosc
fosc
fosc
2.5 / fc (max.)
fc
The high-frequency reference clock is fosc, and ports
P00 and P01 are used as I/O ports.
Ports P00 and P01 are set as oscillation pins.
The high-frequency clock oscillation circuit is warming
up.
The high-frequency reference clock is being switched
to fc.
The high-frequency reference clock has been switch-
ed to fc.
State
TMP89FM42A