tmp89fm42a TOSHIBA Semiconductor CORPORATION, tmp89fm42a Datasheet - Page 207

• Manufacturer Part Number: tmp89fm42a
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14.4
Functions
RA005
Table 14-5 8-bit Timer Mode Resolution and Maximum Time Setting
T00MOD
<TCK0>
000
001
010
011
100
101
110
111
of the T00MOD<DBE0> setting.
(Example) Operate TC00 in the 8-bit timer mode with the operation clock of fcgck/2
SYSCR1<DV9CK>
When a read instruction is executed on T00REG, the last value written into T00REG is read out, regardless
NORMAL1/2 or IDLE1/2 mode
fcgck/2
fcgck/2
fcgck/2
fcgck/2
fcgck/2
fcgck/2
fcgck/2
fcgck
= "0"
be longer than the selected time. If the value set to T00REG is equal to the up counter value, the
match detection is executed immediately after data is written into T00REG. Therefore, the interrupt
request interval may not be an integral multiple of the source clock (Figure 14-3). If these are
problems, enable the double buffer.
immediately stored in T00REG.
11
10
8
6
4
2
μs intervals (fcgck = 10 MHz)
When a write instruction is executed on T00REG while the timer is stopped, the set value is
LD
DI
SET
EI
LD
LD
SET
Source clock [Hz]
SYSCR1<DV9CK>
fcgck/2
fcgck/2
fcgck/2
fcgck/2
fcgck/2
fcgck
= "1"
fs/2
fs/2
4
3
8
6
4
2
(POFFCR0),0x10
(EIRH).4
(T00MOD),0xE8
(T00REG),0xA0
(T001CR).0
SLEEP1 mode
SLOW1/2 or
fs/2
fs/2
fs/2
Page 188
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4
3
2
fcgck=10MHz
; Sets TC001EN to "1"
; Sets the interrupt master enable flag to "disable"
; Sets the INTTC00 interrupt enable register to "1"
; Sets the interrupt master enable flag to "enable"
; Selects the 8-bit timer mode and fcgck/2
; Sets the timer register (64μs / (2
; Starts TC00
204.8μs
102.4μs
25.6μs
400ns
200ns
100ns
6.4μs
1.6μs
Resolution
fs=32.768kHz
488.2μs
244.1μs
122.1μs
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2
[Hz] and generate interrupts at 64
fcgck=10MHz
2
/fcgck) = 0xA0)
52.2ms
26.1ms
25.5μs
408μs
102μs
6.5ms
1.6ms
Maximum time setting
51μs
2
TMP89FM42A
fs=32.768kHz
124.5ms
62.3ms
31.1ms
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