tmp89fm42a TOSHIBA Semiconductor CORPORATION, tmp89fm42a Datasheet - Page 237

• Manufacturer Part Number: tmp89fm42a
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

15.3
Function
RA000
15.3
15.3.1
15.3.2
15.3.3
Real time clock control register
(0x0FC8)
RTCCR
Note 1: fs: Low-frequency clock [Hz]
Note 2: RTCCR<RTCSEL> can be rewritten only when RTCCR<RTCRUN> is "0". If data is written into RTCCR<RTCSEL>
Note 3: If the real time clock is enabled and when 1) SYSCR2<XTEN> is cleared to "0" to stop the low-frequency clock
Function
is not being used.
this renders the real time clock unusable. Setting POFFCR2<RTCEN> to "1" enables the basic clock supply to
real time clock and allows the real time clock to operate.
using the real time clock for the first time, be sure to set POFFCR2<RTCEN> to "1" in the initial setting of the
program (before the real time clock control registers are operated).
may operate unexpectedly.
disables the real time clock operation.
Real time clock has the low power consumption registers (POFFCR2) that save power when the real time clock
Setting POFFCR2<RTCEN> to "0" disables the basic clock supply to real time clock to save power. Note that
After reset, POFFCR2<RTCEN> are initialized to "0", and this renders the real time clock unusable. When
Do not change POFFCR2<RTCEN> to "0" during the real time clock operation. Otherwise real time clock
Setting RTCCR<RTCRUN> to "1" enables the real time clock operation. Setting RTCCR<RTCRUN> to "0"
RTCCR<RTCRUN> is cleared to "0" just after reset release.
The interrupt generation interval can be selected at RTCCR<RTCSEL>.
Low Power Consumption Function
Enabling/disabling the real time clock operation
Selecting the interrupt generation interval
when RTCCR<RTCRUN> is "1", the existing data remains effective. RTCCR<RTCSEL> can be rewritten at the
same time as enabling the real time clock, but it cannot be rewritten at the same time as disabling the real time
clock.
oscillation circuit or 2) the operation is changed to the STOP mode or the SLEEP0 mode, the data in
RTCCR<RTCSEL> is maintained and RTCCR<RTCRUN> is cleared to "0".
Read/Write
Bit Symbol
After reset
RTCRUN
RTCSEL
Selects the interrupt generation interval
Enables/disables the real time clock opera-
tion
R
7
0
-
R
6
0
-
R
5
0
Page 218
-
R
4
0
-
000 : 2
001 : 2
010 : 2
011 : 2
100 : 2
101 : 2
110 : 2
111 : 2
0 : Disable
1 : Enable
15
14
13
12
11
10
9
8
/fs (15.62 [ms] @fs=32.768kHz)
/fs (7.81 [ms] @fs=32.768kHz)
/fs (1.000 [s] @fs=32.768kHz)
/fs (0.500 [s] @fs=32.768kHz)
/fs (0.250 [s] @fs=32.768kHz)
/fs (125.0 [ms] @fs=32.768kHz)
/fs (62.50 [ms] @fs=32.768kHz)
/fs (31.25 [ms] @fs=32.768kHz)
3
0
RTCSEL
R/W
2
0
1
0
TMP89FM42A
RTCRUN
R/W
0
0