tmp89fm42a TOSHIBA Semiconductor CORPORATION, tmp89fm42a Datasheet - Page 251

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tmp89fm42a

Manufacturer Part Number
tmp89fm42a
Description
8 Bit Microcontroller
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

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16.8
Transfer Baud Rate
RA001
16.8.1
16.8.1.1
Note 1: The overall error from the basic baud rate must be within ±3%. Even if the overall error is within ±3%, the communication
Transfer baud rate calculation method
number of RT clocks per bit can be changed in a range of 15 to 17 clocks by changing UART0CR2<RTSEL>.
The RT clock is the transfer base clock, which is the pulses obtained by counting the clock selected at
UART0CR1<BRG> the number of times of (UART0DR set value) + 1. Especially, when
UART0CR2<RTSEL> is set to "0y001" or "0y011", two types of RT clocks alternate at each bit, so that the
pseudo baud rates of RT × 15.5 clocks and RT × 16.5 clocks can be generated. The number of RT clocks per
bit of transfer frame is shown in Figure 16-4.
"0x19", the baud rate calculated using the formula in Figure 16-4 is expressed as:
may fail due to factors such as frequency errors in external controllers (for example, a personal computer) and oscillators
and the load capacity of the communication pin.
The bit width of transmitted/received data can be finely adjusted by changing UART0CR2<RTSEL>. The
For example, when fcgck is 4 [MHz], UART0CR2<RTSEL> is set to "0y000" and UART0DR is set to
fcgck / (16 × (UART0DR + 1) = 9615 [baud]
These settings generate a baud rate close to 9600 [baud] (+0.16%).
Bit width adjustment using UART0CR2<RTSEL>
Table 16-7 Set Values of UART0DR and UART0CR2<RTSEL> for Transfer
Basic baud
[baud]
rate
300
150
134
110
75
Baud Rates (fs=32.768 kHz, UART0CR2<RXDNC>=0y00)
UART0DR
UART0DR
UART0DR
UART0DR
UART0DR
Register
RTSEL
RTSEL
RTSEL
RTSEL
RTSEL
Error
Error
Error
Error
Error
Page 232
Operating frequency
32.768 kHz
(+0.67%)
(+0.67%)
(+0.30%)
(+0.44%)
(-1.20%)
0y011
0y011
0y001
0y001
0y010
0x0D
0x0E
0x1C
0x06
0x11
TMP89FM42A

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