stc3800 Connor-Winfield VCXOs, stc3800 Datasheet - Page 45

• Manufacturer Part Number: stc3800
• Description: Integrated - Stratum 3e Timing Source
• Manufacturer: Connor-Winfield VCXOs

Application Notes continued
Register Access Automatic Control
and described in the Register Access Manual Control section. The Bandwidth_PBO register write operation is also
the same.
MHz and when BITS_Sel = 0, the BITS frequency is 2.048 MHz.
device state.
the application through the bus interface (see Application Notes, General, Configuration Data section). Tie Dmode
“High” for EEPROM pump, and “Low” for register pump.
Notes, General, Reading and Writing EEPROM section.
input reference frequencies may be read from bits 7-4 of the Ref(1-8)_Frq_Priority registers. With automatic reference
selection, the device (In master mode) also performs operational mode selection (Locked, Hold Over, and Free Run)
automatically, as shown in Figure 8.
register.
to bits 4 and 5 of the Ctl_Mode register (0x04), as shown below:
the register value multiple (valid range is 1 - 15) of the Sync_Clk clock period. The same pulse width is applied to both
Sync_8K and Sync_2K. For example, if Sync_Clk is at 19.44 MHz and the desired pulse width is 206nS, write
FR_Pulse_Width to 0000 0100 (4 x 51.5nS).
For Register Access Automatic Control, the interfaces, reset, and bus operations are the same as shown in Figure 13
The BITS clock output frequency is selected by the BITS_Sel pin. When BITS_Sel = 1, the BITS frequency is 1.544
Reset may be pulled low for a minimum of 100nS during chip start-up (or any other desired time) to initialize the full
Following any reset, device configuration data must be pumped, either automatically from the external EEPROM, or by
If the optional EEPROM is equipped, EEPROM data may be read or written via the bus interface. See Application
Select automatic reference frequency selection by writing bit 1 of the register Ctl_Mode (0x04) to 0. The auto-detected
Individual references may be enabled or disabled for use by writing the appropriate values to the Ref_Mask (0x0b)
Select 50% duty cycle or variable pulse width for the Sync_8K and Sync_2K output by writing the appropriate values
In variable pulse width mode, the desired pulse width is written to register FR_Pulse_Width (0x10). The pulse width is
Pulse Width Control
Sync_2K and Sync_8K 50% duty cycle
Sync_2K 50% duty cycle, Sync_8K variable pulse width
Sync_2K variable pulse width, Sync_8K 50% duty cycle
Sync_2K and Sync_8K variable pulse width
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved
Preliminary Data Sheet #: TM061
Reg. 0x03 BITS 5-4
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Specifications subject to change without notice
Rev: P06 Date: 11/22/04