stc3800 Connor-Winfield VCXOs, stc3800 Datasheet - Page 11

• Manufacturer Part Number: stc3800
• Description: Integrated - Stratum 3e Timing Source
• Manufacturer: Connor-Winfield VCXOs

Detailed Description continued
Control Modes
reference, operational modes can be accessed from either the bus interface or external device pins. Master/slave mode
can only be controlled by M/S pin.
configurations.
and reference input selection may be provided by direct hardware pin inputs Sel0-3 (see Table 5) and the
corresponding register access becomes read-only. When HM_Ref is disabled (=0), reference selection and operational
mode control is via register access.
hardware control of operational mode and reference selection are as shown in the table below:
Peripherals section.
DPLL configuration data. This data may come from either an external EEPROM, or the bus interface. The Dmode pin
selects the source for configuration data, 0 = from the bus interface, 1 = from the EEPROM. If the source is an
EEPROM, devices pre-loaded with the configuration data are available from Connor-Winfield (See Application Notes,
External Component Selection section). Data may also be loaded into or read from the EEPROM via the bus interface
(See Application Notes, Reading and Writing EEPROM Data section).
data is available from Connor-Winfield as a file and is loaded per the procedure described in the Application Note,
Configuration Data section.
Parallel or serial bus interfaces are provided to access STC3800 internal control and status registers.The selected
Hardware Control
The HM_Ref pin enables hardware control of reference selection and operational mode. When it is a “1”, mode control
The M/S pin determines master or slave mode. 1=Master, 0=Slave. In master mode and with HM_Ref = 1, the
In slave mode, the operational mode is “locked” and the reference is the Xref input.
See Register Descriptions and Operation and Application section: Control Modes for more details.
The VC_Sel pin determines if the VCXO input to the chip is TTL or PECL, 1 = TTL, 0 = PECL. See Application Notes,
Following any device reset, either via power-up or operation of the Reset pin, the device needs to be loaded with its
If the data is to be application provided on reset through the bus interface (i.e. the optional EEPROM is not equipped), the
Sel3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Sel2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
– The device may be configured for direct pin control over key functions for simple hardwired
Pin
Sel1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Hardware Reference Selection and Mode Control
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved
Preliminary Data Sheet #: TM061
Sel0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Table 5
Hold Over
Hold Over
Hold Over
Hold Over
Hold Over
Hold Over
Hold Over
Free Run
Locked
Locked
Locked
Locked
Locked
Locked
Locked
Locked
Mode
Page 11 of 48
Specifications subject to change without notice
Function
Rev: P06 Date: 11/22/04
Reference
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
2
3
4
5
6
7
8