stc3800 Connor-Winfield VCXOs, stc3800 Datasheet - Page 42

• Manufacturer Part Number: stc3800
• Description: Integrated - Stratum 3e Timing Source
• Manufacturer: Connor-Winfield VCXOs

Application Notes continued
Register Access Manual Control
In Register Control Mode, far more internal device information is available. However, Operational mode and Reference
Selection may still be performed manually. The control configuration for this mode of operation is shown in Figure 14:
In Register Access Manual Control Operation, the hardware control pin, HM_Ref, is tied low.
Reset may be pulled low for a minimum of 200nS during chip start-up (or any other desired time) to initialize the full
device state.
Following any reset, device configuration data must be pumped, either automatically from the external EEPROM, or by
the application through the bus interface (see Application Notes, General, Configuration Data section). Tie Dmode
“High” for EEPROM pump, and “Low” for register pump.
If the optional EEPROM is equipped, EEPROM data may be read or written via the bus interface. See Application
Notes, General, Reading and Writing EEPROM section.
The BITS clock output frequency is selected by the BITS_Sel pin. When BITS_Sel = 1, the BITS frequency is 1.544
MHz and when BITS_Sel = 0, the BITS frequency is 2.048 MHz
Bus access may be either in parallel or SPI mode. Bmode is connected “high” for parallel bus and “low” for SPI
operation. Parallel bus operation uses CS, ALE, R/W, RDY, and AD0-7, as described in the Register Control section,
Figures 3 and 4, and Table 6. SPI uses CS, SCLK, SDI, and SDO, as described in the Register Control section, Figures
5 and 6, and Table 7.
I/O
Bus Interface
frequency select
1 = 1.544MHz
0 = 2.048MHz
BITS output
Bus Mode:
1 = Parallel
0 = SPI
Reset
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved
Register Access Manual Control Interfaces
Preliminary Data Sheet #: TM061
8
Bmode
CS
ALE or SCLK
R/W or SDI
AD0-7
BITS_Sel
HM_Ref
RDY or SDO
Reset
Figure 14
STC3800
Hold_Avail
Page 42 of 48
INTR
LOS
LOL
Specifications subject to change without notice
Rev: P06
(Optional
Outputs
Use)
Date: 11/22/04