stc3800 Connor-Winfield VCXOs, stc3800 Datasheet - Page 33

• Manufacturer Part Number: stc3800
• Description: Integrated - Stratum 3e Timing Source
• Manufacturer: Connor-Winfield VCXOs

Application Notes continued
Sync_Clk outputs to the other device’s Xref input (See Figure 10). Note that 8 kHz frame phase alignment is
maintained across a master/slave pair of devices only if Sync_8K is used as the cross couple signal.
Slave switch occurs, synchronization would continue with the same reference. The references may be driven by the
same signal directly or via separate drivers, as the redundancy of that part of the system requires. Distribution path
lengths are not critical here, as a phase build-out will occur when a device switches from slave to master.
However, to accommodate path length delays, the STC3800 provides a programmable phase skew feature, which
allows the application to offset the output clocks from the cross-reference signal by up to ± 32 ns, in 0.25nS increments.
This offset may therefore be programmed to exactly compensate for the actual path length delay associated with the
particular application’s cross-reference traces. The offset may further be adjusted to accommodate any output clock
distribution path delay differences. Phase offset is programmed by writing to the Phase_Offset register, and is typically
a one-time device initialization function. (See register description and Register Access Control sections). Thus,
master/slave switches with the STC3800 devices may be accomplished with near-zero phase hits.
the cross couple path lengths at a minimum and relatively equal in length, as the path length will appear as a phase hit
in the slave clock output when a master/slave switch occurs in a Hardware Control configuration.
Master/Slave Configuration
Additionally, the reference inputs for each device would typically be correspondingly the same, so that when a Master/
The path lengths of the two Sync_8K or Sync_Clk to Xref signals is of interest, however. They need not be the same.
For applications that use Hardware Control only (i.e. phase offset programming is not available), it is desirable to keep
Reference 1 In
Reference n In
– A pair of devices are interconnected by cross-coupling their respective Sync_8K or
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved
Preliminary Data Sheet #: TM061
Master / Slave Configuration
Figure 10
Refn
Xref
Ref1
Xref
Ref1
Refn
STC3500
STC3800
STC3800
Sync_Clk
BITS_Clk
Sync_Clk
Sync_2K
Sync_8K
BITS_Clk
Sync_8K
Sync_2K
1
2
Page 33 of 48
2 kHz multi-frame sync
BITS clock output
Synchronized clock output
Synchronized clock output
2 kHz multi-frame sync
BITS clock output
8 kHz
Specifications subject to change without notice
8 kHz
Rev: P06 Date: 11/22/04