stc3800 Connor-Winfield VCXOs, stc3800 Datasheet - Page 40

• Manufacturer Part Number: stc3800
• Description: Integrated - Stratum 3e Timing Source
• Manufacturer: Connor-Winfield VCXOs

Application Notes continued
Control Modes
The STC3800 device may be controlled and interfaced in a pure hardware mode with pin signals, or via SPI or parallel
bus/register access. With register access, the device can in turn be operated in a manual control mode, or automatic
control and reference selection mode. Hardware mode is most suitable for simple environments where minimal external
intelligence is desired. Register access provides more detailed visibility and control for references and general
synchronization operation. Stratum 3E operation requires register access to set the appropriate PLL bandwidth and to
enable phase build out.
These three main operating environments are detailed as follows:
Hardware Control
Reset may be pulled low for a minimum of 200nS during chip start-up (or any other desired time) to initialize the full
device state. However, power-up will also perform a reset, so in a minimal configuration, Reset may be tied input high.
For Hardware Control (no bus interface use), the device configuration data must be provided via the external EEPROM,
Dmode is tied “high”, and pump is completed automatically after any reset.
The BITS clock output frequency is selected by the BITS_Sel pin. When BITS_Sel = 1, the BITS frequency is 1.544
MHz, and when BITS_Sel = 0, the BITS frequency is 2.048 MHz.
M/S - Determines the master or slave mode. Set to “1” for a master, and “0” for a slave. Master/slave switches should
be performed with minimal delay between switching the states of each of the two devices. This can be easily
accomplished, for example, by controlling the master/slave state with a single signal, coupled to one of the devices
through an inverter.
For simplex operation, the device should be in Master mode - set M/S to “1”.
HM_Ref - Set to “1” for hardware control of reference selection and operational mode.
I/O
Bus Interface
frequency select
– The device interfaces for hardware control are shown in Figure 13.
1 = 1.544 MHz
0 = 2.048 MHz
BITS output
Bus Mode:
1 = Parallel
0 = SPI
Interrupt
Reset
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved
Preliminary Data Sheet #: TM061
Hardware Control Interfaces
8
Bmode
CS
ALE or SCLK
R/W or SDI
AD0-7
HM_Ref
RDY or SDO
INTR
BITS_Sel
Reset
Figure 13
STC3800
Hold_Avail
Page 40 of 48
INTR
LOS
LOL
Specifications subject to change without notice
Rev: P06
(Optional Use)
Outputs
Date: 11/22/04