stc3800 Connor-Winfield VCXOs, stc3800 Datasheet - Page 21

• Manufacturer Part Number: stc3800
• Description: Integrated - Stratum 3e Timing Source
• Manufacturer: Connor-Winfield VCXOs

Register Descriptions and Operation continued
MS_Phase_Offset, 0x0e (R/W)
In slave mode, the slave’s outputs may be phase shifted -32nS to +31.75nS in .25nS increments, relative to Xref according to the
contents of the MS_Phase_Offset register, to compensate for the path length of the Sync_8K or Sync_Clk to Xref connection.
respective path lengths of each Sync_8K or Sync_Clk to Xref connection, to ensure that the same relative output signal phases
will persist through master/slave switches.
Calibration, 0x0f (R/W)
To digitally calibrate the synthesized free running clock from the OCXO/TCXO, this register is written with a value corresponding to
the known frequency offset of the oscillator from the nominal center frequency.
Fr_Pulse_Width, 0x10 (R/W)
Bits 4 and 5 of the Ctl_Mode register determine if the Sync_8K 8 kHz and/or Sync_2K 2 kHz outputs are 50% duty cycle or pulsed
(high going) outputs. When they are pulsed, the Fr_Pulse_Width register determines the width. Width is the register value multiple
of the Sync_Clk clock period. Valid values are 1 - 15. The same pulse width is applied to both Sync_8K and Sync_2K. Reset
default is 0001. Writing to 0000 maps to 0001.
DPLL_Status, 0x11 (R)
Bit 0 indicates the presence of a signal on the selected reference.
operation, or lock is lost after previously having been established. LOL will not be asserted for automatic reference switches.
a good reference. It will indicate “not locked” if lock is lost.
If a phase offset is used, then the two STC3800 devices would typically be written to the appropriate phase offset values for the
Bit 1 indicates a loss of lock (LOL). Loss of lock will be asserted if lock is not achieved within the specified time for the stratum of
Bit 2 indicates successful phase lock. It will typically be set in <100 seconds for stratum 3 and <700 seconds for stratum 3E, with
Bit 3 indicates if a Hold Over history is available.
Bit 4 indicates when a new Hold Over history has been successfully built and transferred to the active Hold Over history.
The 2’s complement value of phase offset between Sync_8K or Sync_Clk and Xref, ranges from -32 nS to +31.75 nS
2’s complement value of local oscillator digital calibration in 0.05 ppm resolution
Reserved
Reserved
Bit 7 ~ Bit 5
Positive Value: Sync_8K or Sync_Clk rising edge leads Xref
Negative Value: Sync_8K or Sync_Clk rising edge lags Xref
Bit 7 ~ Bit4
Bit 4
Hold Over
Build
Complete
1: Hold Over
0: Hold Over
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved
history build
complete
history build
not complete
Preliminary Data Sheet #: TM061
Hold Over
Available
1: Avail.
0: Not avail.
Bit 3
Pulse width for Sync_8K and Sync_2K clock outputs,
1-15 multiples of the Sync_Clk clock period.
Bit 7 ~ Bit 0
Bit 7 ~ Bit 0
0: Not locked
Locked
1: Locked
Bit 3 ~ Bit 0
Bit 2
Page 21 of 48
Loss of Lock
1: Loss of Lock
0: No loss of lock
Specifications subject to change without notice
Bit 1
Rev: P06 Date: 11/22/04
Loss of Signal
1: No activity
0: Active ref-
present
Bit 0
on active
reference
erence signal