pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 52

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Table 2
Pin No.
69
119,
130,
47,
61
System Interface Receive
9
8
12
Data Sheet
Name
SEC
SEC
FSC
RCLK(1:4)
RDO1
SCLKR1
RDO2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin Type
I
O
O
O
O
I/O
O
Buffer
Type
PU
–
–
–
–
PU
–
Function
One-Second Timer Input
A pulse with logical high level for at least two 2.048 MHz
cycles triggers the internal one-second timer. After reset this
pin is configured to be an input. If not connected, an internal
pullup transistor ensures high input level (see register
GPC1).
One-Second Timer Output
Activated high every second for two 2.048 MHz clock cycles.
8 kHz Frame Synchronization
The optionally synchronization pulse is active high or low for
one 2.048/1.544 MHz cycle (pulse width = 488 ns for E1and
648 ns or T1/J1).
Receive Clock Out, ports 1 to 4
After reset this ports are configured to be internally pulled up
weakly. Setting of register bit PC5.CRP will switch this ports
to be active outputs.
Receive Data Out, port 1
Received data that is sent to the system highway. Clocking
of data is done with the rising or falling edge (SIC3.RESR) of
SCLKR1, if the receive elastic store is bypassed. The delay
between the beginning of time slot 0 and the initial edge of
SCLKR1 (after SYPR goes active) is determined by the
values of registers RC1 and RC0.
If received data is shifted out with higher (more than
2.048/1.544 Mbit/s) data rates, the active channel phase is
defined by bits SIC2.SICS(2:0). During inactive channel
phases RDO1 is cleared (driven to low level, not tristate).
System Clock Receive, port 1
Working clock for the receive system interface with a
frequency of 16.384/8.192/4.096/2.048 MHz in E1 mode and
16.384/8.192/4.096/2.048 MHz (SIC2.SSC2 = 0
12.352/6.176/3.088/1.544 MHz (SIC2.SSC2 = 1
mode. If the receive elastic store is bypassed, the clock
supplied on this pin is ignored, because RCLK is used to
clock the receive system interface.
If SCLKR1 is configured to be an output, the internal working
clock of the receive system interface sourced by DCO-R or
RCLK is output.
Receive Data Out, port 2
Received data that is sent to the system highway. Clocking
of data is done with the rising or falling edge (SIC3.RESR) of
SCLKR2, if the receive elastic store is bypassed. The delay
between the beginning of time slot 0 and the initial edge of
SCLKR2 (after SYPR goes active) is determined by the
values of registers RC1 and RC0.
If received data is shifted out with higher (more than
2.048/1.544 Mbit/s) data rates, the active channel phase is
defined by bits SIC2.SICS(2:0). During inactive channel
phases RDO2 is cleared (driven to low level, not tristate).
52
Rev. 1.3, 2006-01-25
Pin Descriptions
QuadLIU
PEF 22504
B
B
) or
) in T1/J1
TM