pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 27

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Table 1
Pin No.
P2
P3
P13
P12
Clock Signals
B4
Data Sheet
I/O Signals (cont’d)for P/PG-LBGA-160-1
Name
XL1.3
XOID3
XL2.3
XL1.4
XOID4
XL2.4
MCLK
Pin Type Buffer
O
(analog)
O
O
(analog)
O
(analog)
O
O
(analog)
I
Type
–
–
–
–
–
–
–
27
Function
Transmit Line 1, port 3
Analog output to the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit MR0.XC1 is set and
XPM2.XLT is cleared.
Transmit Optical Interface Data, port 3
Data in CMI code is shifted out with 50% or 100% duty
cycle on both transitions of XCLK3 according to the CMI
coding. Output polarity is selected by bit LIM0.XDOS
(after reset: data is sent active high). The single-rail
mode is selected if LIM1.DRS is set and MR0.XC1 is
cleared. After reset this pin is in high-impedance state
until register LIM1.DRS is set and XPM2.XLT is cleared.
Transmit Line 2, port 3
Analog output for the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit MR0.XC1 is set and
XPM2.XLT is cleared.
Transmit Line 1, port 4
Analog output to the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit MR0.XC1 is set and
XPM2.XLT is cleared.
Transmit Optical Interface Data, port 4
Data in CMI code is shifted out with 50% or 100% duty
cycle on both transitions of XCLK4 according to the CMI
coding. Output polarity is selected by bit LIM0.XDOS
(after reset: data is sent active high). The single-rail
mode is selected if LIM1.DRS is set and MR0.XC1 is
cleared. After reset this pin is in high-impedance state
until register LIM1.DRS is set and XPM2.XLT is cleared.
Transmit Line 2, port 4
Analog output for the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit MR0.XC1 is set and
XPM2.XLT is cleared.
Master Clock
A reference clock of better than ±32 ppm accuracy in
the range of 1.02 to 20 MHz must be provided on this
pin. The QuadLIU
clocks from this master
(see registers GCM(6:1)).
TM
internally derives all necessary
Rev. 1.3, 2006-01-25
Pin Descriptions
QuadLIU
PEF 22504
TM