pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 246

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

must be programmed before the activation procedure of the PCM line starts. Such procedures are specified in
ITU-T recommendations (e.g. fault conditions and consequent actions). Setting optional parameters primarily
makes sense when basic operation via the PCM line is guaranteed.
important parameters in terms of signals and control bits which are to be programmed in one of the above steps.
The sequence is recommended but not mandatory. Accordingly, parameters for the basic and operational set up,
for example, can be programmed simultaneously. The bit MR1.PMOD must always be kept high (otherwise E1
mode is selected). J1 mode is selected by additionally setting RC0.SJR = ´1´.
Features like channel loop-back, idle channel activation, clear channel activation, extensions for signaling support,
alarm simulation, etc. are activated later. Transmission of alarms (e.g. AIS, remote alarm) and control of
synchronization in connection with consequent actions to remote end and internal system depend on the activation
procedure selected.
Table 77
Basic Set Up
Master clocking mode
T1/J1 mode select
Clock system configuration
Specification of line interface
Specification of transmit pulse mask XPM(2:0) or TXP(16:1)
Line interface coding
Loss-of-signal detection/recovery
conditions
AIS to framer interface
Multi Function Port selection
Note: Read access to unused register addresses: value should be ignored. Write access to unused register
Specific T1/J1 Configuration
The following is a suggestion for a basic configuration to meet most of the T1/J1 requirements. Depending on
different applications and requirements any other configuration can be used.
Table 78
Register
GPC6.COMP_DIS = ´1´
MR2.DAIS = ´1´
LOOP.RTM = ´1´
MR4.TM = ´1´
MR5.XTM = ´1´
CCB(3:1) = ´FF
MR0.XC0/1
MR0.RC0/1
LIM1.DRS
CCB(3:1)
DIC3.CMI
Data Sheet
addresses: should be avoided, or set to ´00
type read/write
Configuration Parameters (T1/J1)
Line Interface Configuration (T1/J1)
H
‘
Function
Sets the QuadLIU
Disables AIS insertion into the data stream (necessary for proper operation)
Sets the receive dual elastic store in a “free running” mode (necessary for proper
operation)
Enables transparent mode (necessary for proper operation)
Sets the transmitter in a “free running” mode (necessary for proper operation)
“Clear Channel” mode is selected (necessary for proper operation only if AMI code is
selected)
The QuadLIU
digital line interface. For the analog line interface the codes AMI (with and without bit
7stuffing) and B8ZS are supported. For the digital line interface modes (dual- or
single-rail) the QuadLIU
and without B8ZS precoding).
T1
PCD, PCR, LIM1, LIM2
MR2.XAIS
GCM(6:1) according to external MCLK clock frequency
MR1.PMOD = ´1´,
CMR(3:1), GPC1; CMR(6:4) and GPC(6:2)
LIM0, LIM1,
MR0.XC(1:0), MR0.RC(1:0)
PC(3:1)
TM
supports requirements for the analog line interface as well as the
TM
into a defined mode (necessary for proper operation)
H
TM
´. All control registers (except XS(12:1), CMDR, DEC) are of
supports AMI (with and without bit 7 stuffing), B8ZS (with
246
Table 77
J1
MR1.PMOD = ´1´,
gives an overview of the most
Operational Description
Rev. 1.3, 2006-01-25
QuadLIU
PEF 22504
TM