pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 203

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Code Violation Counter Lower Byte
CVCL
Code Violation Counter Lower Byte
Field
CV7
CV6
CV5
CV4
CV3
CV2
CV1
CV0
Data Sheet
Bits
7
6
5
4
3
2
1
0
Type
r
r
r
r
r
r
r
r
Description
Code Violations
If the HDB3 or the CMI code with HDB3-precoding is selected, the 16-bit
counter is incremented when violations of the HDB3 code are detected.
The error detection mode is determined by programming the bit
MR0.EXTD. If simple AMI coding is enabled (MR0.RC(1:0) = ´01
bipolar violations are counted. The error counter does not roll over.During
alarm simulation, the counter is incremented every four bits received up
to its saturation. Clearing and updating the counter is done according to
bit MR1.ECM. If this bit is reset the error counter is permanently updated
in the buffer. For correct read access of the error counter bit DEC.DCVC
has to be set. With the rising edge of this bit updating the buffer is stopped
and the error counter is reset. Bit DEC.DCVC is reset automatically with
reading the error counter high byte. If MR1.ECM is set every second
(interrupt ISR3.SEC) the error counter is latched and then automatically
reset. The latched error counter state should be read within the next
second.
Register DescriptionCode Violation Counter Lower Byte
Offset
xx52
203
H
Rev. 1.3, 2006-01-25
QuadLIU
PEF 22504
Reset Value
b
´) all
00
TM
H