pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 105

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Figure 38
3.9.5
The received single rail bit stream from pin XDI or dual rail bit stream from the pins XDIP and XDIN are optionally
stored in the transmit elastic buffer, see
buffer. The functions are also equal to the receive side. Programming of the dual transmit buffer size is done by
DIC1.XBS(1:0) in the same way as programming of the dual receive buffer size by DIC1.RBS(1:0), see
The functions of the transmit buffer are:
•
•
•
Writing of received data from XDIP/XDIN is controlled by the internal transmit clock. Selection of FCLKX or FCLKR
is possible, see multiplexer “E” in
FCLKR.)
Reading of stored data is controlled by the clock generated either by the DCO-X circuitry or the externally
generated TCLK. With the de-jittered clock data is read from the dual transmit elastic buffer and are forwarded to
the transmitter. Reporting and controlling of slips is done according to the receive direction. Positive/negative slips
are reported in interrupt status bits ISR4.XSP and ISR4.XSN. If the transmit buffer is bypassed data is directly
transferred to the transmitter.
3.9.6
The transmitter includes a programmable pulse shaper to generate transmit pulse masks according to:
•
•
The transmit pulse shape (U
Data Sheet
Clock adoption between framer transmit clock (FCLKX) and internally generated transmit route clock, see
Chapter
Compensation of input wander and jitter.
Reporting and controlling of slips
For T1: FCC68; ANSI T1. 403 1999, figure 4; ITU-T G703 11/2001, figure 10 (for different cable lengths), see
Figure 64
For E1: ITU-T G703 11/2001, figure 15 (for 0 m cable length) see
(for DCIM mode), see
Receive Line
Interface
Transmit Line
Interface
XL1/XOID1
RL1/ROID
MCLK
XCLK
XL3
XL2
XL4
RL2
3.9.4.
Clocking and Data in Remote Loop Configuration
Dual Transmit Elastic Buffer
Programmable Pulse Shaper and Line Build-Out
and
Equalizer
Figure 40
Clocking Unit
Master
Figure 39
PULSE
for measurement configuration were R
Figure
) is programmed either
DAC
for measurement configuration were R
Shaper,
Pulse
LBO
Figure
36. (If the DCO-R output is selected, the DCO_R output is also output at
Recovery
Clock &
Data
DPLL
36. The tansmit elastic buffer is organized as the receive elastic
105
Buffer
JATT
Decoder
Encoder
H
load
Figure
= 100
DCO-X
load
63; ITU-T G703 11/2001, figure 20
= 120
Automatic Transmit
Clock Switching
recovered
receive clock
G
or R
Functional Description
Q LIU _rem ote_loop_c loc k ing
F
Rev. 1.3, 2006-01-25
load
= 75
E
%
from
DCO-R
QuadLIU
PEF 22504
XDATA
FCLKR
FCLKX
TCLK
Table
RDATA
26:
TM