mc68hc908gr8vp Freescale Semiconductor, Inc, mc68hc908gr8vp Datasheet - Page 73

• Manufacturer Part Number: mc68hc908gr8vp
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by systems that do not
require an indicator of the lock condition for proper operation. Such systems typically operate well below
f
The following conditions apply when in manual mode:
7.3.6 Programming the PLL
The following procedure shows how to program the PLL.
Freescale Semiconductor
BUSMAX
1. Choose the desired bus frequency, f
2. Calculate the desired VCO frequency (four times the desired bus frequency).
3. Choose a practical PLL (crystal) reference frequency, f
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•
•
•
•
•
•
The LOCK bit is set when the VCO frequency is within a certain tolerance and is cleared when the
VCO frequency is out of a certain tolerance. (See
more information.)
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling
the LOCK bit. (See
ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual
mode, the ACQ bit must be clear.
Before entering tracking mode (ACQ = 1), software must wait a given time, t
7.8 Acquisition/Lock Time
control register (PCTL).
Software must wait a given time, t
clock source to CGMOUT (BCS = 1).
The LOCK bit is disabled.
CPU interrupts from the CGMC are disabled.
Typically, the reference crystal is 32.768 kHz and R = 1.
Frequency errors to the PLL are corrected at a rate of f
this rate must be as fast as possible. The VCO frequency must be an integer multiple of this rate.
The relationship between the VCO frequency, f
P, the power of two multiplier, and N, the range multiplier, are integers.
In cases where desired bus frequency has some tolerance, choose f
either by other module requirements (such as modules which are clocked by CGMXCLK), cost
requirements, or ideally, as high as the specified range allows. See
Specifications. Choose the reference divider, R = 1. After choosing N and P, the actual bus
frequency can be determined using equation in 2 above.
.
The round function in the following equations means that the real number
should be rounded to the nearest integer number.
7.5.1 PLL Control
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
Specifications), after turning on the PLL by setting PLLON in the PLL
f
AL
VCLKDES
f
, after entering tracking mode before selecting the PLL as the
VCLK
BUSDES
Register.)
=
NOTE
=
.
2
----------- f
P
R
4
N
×
VCLK
(
f
BUSDES
RCLK
7.8 Acquisition/Lock Time Specifications
, and the reference frequency, f
RCLK
)
RCLK
/R. For stability and lock time reduction,
, and the reference clock divider, R.
Chapter 23 Electrical
RCLK
to a value determined
ACQ
Functional Description
(see
RCLK
, is
for
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