mc68hc908gr8vp Freescale Semiconductor, Inc, mc68hc908gr8vp Datasheet - Page 71

• Manufacturer Part Number: mc68hc908gr8vp
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

7.3.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the
input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration
module (SIM) or the OSCSTOPENB bit in the CONFIG register enable the crystal oscillator circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal
frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing for operation. The duty cycle of
CGMXCLK is not guaranteed to be 50% and depends on external factors, including the crystal and related
external components. An externally generated clock also can feed the OSC1 pin of the crystal oscillator
circuit. Connect the external clock to the OSC1 pin and let the OSC2 pin float.
7.3.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending
on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes
either automatically or manually.
7.3.3 PLL Circuits
The PLL consists of these circuits:
The operating range of the VCO is programmable for a wide range of frequencies and for maximum
immunity to external noise, including supply and CGM/XFC noise. The VCO frequency is bound to a
range from roughly one-half to twice the center-of-range frequency, f
CGM/XFC pin changes the frequency within this range. By design, f
center-of-range frequency, f
(L × 2
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency,
f
factor, R. The divider’s output is the final reference clock, CGMRDV, running at a frequency,
f
(30 kHz–100 kHz), always set R = 1 for specified performance. With an external high-frequency clock
source, use R to divide the external frequency to between 30 kHz and 100 kHz.
The VCO’s output clock, CGMVCLK, running at a frequency, f
prescale divider and a programmable modulo divider. The prescaler divides the VCO clock by a
power-of-two factor P and the modulo divider reduces the VCO clock by a factor, N. The dividers’
output is the VCO feedback clock, CGMVDV, running at a frequency, f
7.3.6 Programming the PLL
Freescale Semiconductor
RCLK
RDV
•
•
•
•
•
•
•
= f
, and is fed to the PLL through a programmable modulo reference divider, which divides f
E
Voltage-controlled oscillator (VCO)
Reference divider
Frequency prescaler
Modulo VCO frequency divider
Phase detector
Loop filter
Lock detector
)f
RCLK
NOM
.
/R. With an external crystal
NOM
for more information.)
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
, (38.4 kHz) times a linear factor, L, and a power-of-two factor, E, or
VCLK
, is fed back through a programmable
VRS
VRS
VDV
is equal to the nominal
. Modulating the voltage on the
= f
VCLK
/(N × 2
Functional Description
P
). (See
RCLK
by a
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