mc68hc908gr8vp Freescale Semiconductor, Inc, mc68hc908gr8vp Datasheet - Page 134

• Manufacturer Part Number: mc68hc908gr8vp
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Monitor ROM (MON)
Figure 15-2
1 x V
of 9600, as the internal bus frequency is automatically set to the external frequency divided by four.
Enter monitor mode with pin configuration shown in
rising edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins
can change.
Once out of reset, the MCU waits for the host to send eight security bytes. (See Security.) After the
security bytes, the MCU sends a break signal (10 consecutive logic 0s) to the host, indicating that it is
ready to receive a command.
134
V
GND
GND
V
V
GND
V
IRQ
1. External clock is derived by a 32.768 kHz crystal or a 9.8304 MHz off-chip oscillator
2. PTA0 = 1 if serial communication; PTA0 = X if parallel communication
3. PTA1 = 0 → serial, PTA1 = 1 → parallel communication for security code entry
4. DNA = does not apply, X = don’t care
TST
or
X
or
DD
DD
DD
DD
RESET
GND
V
V
V
V
V
V
V
voltage is applied to the IRQ pin. An external oscillator of 9.8304 MHz is required for a baud rate
or
or
TST
TST
TST
DD
DD
DD
DD
shows a simplified diagram of the monitor mode entry when the reset vector is blank and just
$FFFE/
$FFFF
$FFFF
$FFFF
$FFFF
$FFFF
The PTA1 pin must remain at logic 0 for 24 bus cycles after the RST pin
goes high to enter monitor mode properly.
Not
X
X
Table 15-1. Monitor Mode Signal Requirements and Options
OFF
OFF
OFF
OFF
PLL PTB0 PTB1
ON
X
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
X
X
X
X
X
1
X
X
X
X
X
0
External
Clock
9.8304
9.8304
32.768
MHz
MHz
kHz
X
X
X
(1)
CGMOUT
4.9152
4.9152
4.9152
MHz
MHz
MHz
NOTE
—
—
0
Figure 15-1
2.4576
2.4576
2.4576
Freq
MHz
MHz
MHz
Bus
—
—
0
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
COP
by pulling RST low and then high. The
PTA0 PTA1
X
X
X
X
X
X
1
1
1
Communication
For Serial
X
X
X
0
1
0
1
0
1
Rate
Freescale Semiconductor
Baud
9600
9600
9600
DNA
DNA
DNA
—
—
0
(2) (3)
frequency always
PTB0 and PTB1
until reset goes
illegal address
voltages only
monitor code
encounter an
No operation
PLL enabled
(BCS set) in
mode — will
divided by 4
IRQ = V
Enters user
user mode
Comment
required if
External
Enters
reset
high
TST