mc68hc908gr8vp Freescale Semiconductor, Inc, mc68hc908gr8vp Datasheet - Page 127

• Manufacturer Part Number: mc68hc908gr8vp
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Chapter 14
Low-Voltage Inhibit (LVI)
14.1 Introduction
This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the V
and can force a reset when the V
14.2 Features
Features of the LVI module include:
14.3 Functional Description
Figure 14-1
contains a bandgap reference circuit and comparator. Clearing the LVI power disable bit, LVIPWRD,
enables the LVI to monitor V
module to generate a reset when V
stop mode bit, LVISTOP, enables the LVI to operate in stop mode. Setting the LVI 5V or 3V trip point bit,
LVI5OR3, enables V
be configured for 3V operation. The actual trip points are shown in
Freescale Semiconductor
•
•
•
Programmable LVI reset
Selectable LVI trip voltage
Programmable stop mode operation
shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module
After a power-on reset (POR) the LVI’s default mode of operation is 3 V. If
a 5V system is used, the user must set the LVI5OR3 bit to raise the trip
point to 5V operation. Note that this must be done after every POR since
the default will revert back to 3V mode after each POR. If the V
below the 5V mode trip voltage but above the 3V mode trip voltage when
POR is released, the part will operate because V
after a POR. So, in a 5V system care must be taken to ensure that V
above the 5V mode trip voltage after POR is released.
If the user requires 5V mode and sets the LVI5OR3 bit after a POR while
the V
immediately go into reset. The LVI in this case will hold the part in reset until
either V
reset or V
and reset the trip point to 3V operation.
DD
TRIPF
DD
supply is not above the V
DD
goes above the rising 5V trip point, V
to be configured for 5V operation. Clearing the LVI5OR3 bit enables V
decreases to approximately 0 V which will re-trigger the POR
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
DD
voltage. Clearing the LVI reset disable bit, LVIRSTD, enables the LVI
DD
DD
voltage falls below the LVI trip falling voltage, V
falls below the trip point voltage, V
TRIPR
NOTE
for 5V mode, the MCU will
TRIPR
TRIPF
Chapter 23 Electrical
, which will release
defaults to 3V mode
TRIPF
DD
. Setting the LVI enable in
supply is
DD
TRIPF
is
Specifications.
.
DD
TRIPF
pin
127
to