mc68hc908gr8vp Freescale Semiconductor, Inc, mc68hc908gr8vp Datasheet - Page 136

• Manufacturer Part Number: mc68hc908gr8vp
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Monitor ROM (MON)
15.3.2 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
15.3.3 Break Signal
A start bit (0) followed by nine 0 bits is a break signal. When the monitor receives a break signal, it drives
the PTA0 pin high for the duration of two bits and then echoes back the break signal.
15.3.4 Baud Rate
The communication baud rate is controlled by the crystal frequency upon entry into monitor mode. The
divide by ratio is 1024.
If monitor mode was entered with V
was entered with V
32.768 kHz, to 2.4576 MHz. These latter two conditions for monitor mode entry require that the reset
vector is blank.
Table 15-3
standard baud rates can be accomplished using proportionally higher or lower frequency generators. If
using a crystal as the clock source, be aware of the upper frequency limit that the internal clock module
can handle. See
136
lists external frequencies required to achieve a standard baud rate of 9600 BPS. Other
START
23.6 5.0 V Control Timing
BIT
SS
0
on IRQ, then the internal PLL steps up the external frequency, presumed to be
9.8304 MHz
9.8304 MHz
Frequency
32.768 kHz
BIT 0
External
1
2
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
MISSING STOP BIT
BIT 1
Table 15-3. Monitor Baud Rate Selection
3
Figure 15-3. Monitor Data Format
4
DD
Figure 15-4. Break Transaction
BIT 2
on IRQ, then the divide by ratio is also set at 1024. If monitor mode
5
V
IRQ
V
V
6
BIT 3
TST
DD
SS
and
7
23.7 3.0 V Control Timing
BIT 4
2.4576 MHz
2.4576 MHz
2.4576 MHz
Frequency
BIT 5
Internal
2-STOP BIT DELAY BEFORE ZERO ECHO
BIT 6
0
1
BIT 7
2
3
Baud Rate
STOP
BIT
(BPS)
for this limit.
9600
9600
9600
4
START
NEXT
5
BIT
6
Freescale Semiconductor
7