mc68hc908gr8vp Freescale Semiconductor, Inc, mc68hc908gr8vp Datasheet - Page 192

• Manufacturer Part Number: mc68hc908gr8vp
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

System Integration Module (SIM)
19.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out
4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU and memories are released
from reset to allow the reset vector sequence to occur.
At power-on, these events occur:
19.3.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an
internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down
the RST pin for all internal reset sources.
The COP module is disabled if the RST pin or the IRQ pin is held at V
The COP module can be disabled only through combinational logic conditioned with the high voltage
signal on the RST or the IRQ pin. This prevents the COP from becoming disabled as a result of external
noise. During a break state, V
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A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables CGMOUT.
Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow
stabilization of the oscillator.
The RST pin is driven low during the oscillator stabilization time.
The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are
cleared.
CGMXCLK
CGMOUT
PORRST
OSC1
IRST
RST
IAB
CYCLES
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
4096
tst
on the RST pin disables the COP module.
Figure 19-7. POR Recovery
CYCLES
32
CYCLES
32
tst
while the MCU is in monitor mode.
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