stlc5412 STMicroelectronics, stlc5412 Datasheet - Page 8

• Manufacturer Part Number: stlc5412
• Description: 2b1q U Interface Device Enhanced With Dect Mode
• Manufacturer: STMicroelectronics

STLC5412
PIN FUNCTIONS (specific GCI mode)
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Pin
11
12
13
14
15
16
17
18
19
6
7
CONF2
CONF1
TEST2
TEST1
Name
BCLK
PLLD
FSa
FSb
LFS
ES2
ES1
IO4
IO3
IO2
IO1
EC
EC
S0
Bx
S2
S1
Br
In/Out
In, Out
In Out
In Out
In Out
In Out
In Out
Out
Out
Out
Out
In
In
In
In
In
In
In
In
In
In
In
In
Input or Output depending of the configuration. FSa is a 8 KHz clock which
indicates the start of the frame on Bx and Br.
In NT/TE non auto-mode configuration, FSb is a 8 KHz pulse always
indicating the second 64Kbit/sec channel of the frame on Br.
When MO = 0 (LT/NT12 configuration): S0 associated with S1 and S2
selects a GCI channel number on Bx/Br.
Input pin to select a transmission test in all auto mode configurations.
TEST2 is associated with TEST1.
2B+D and GCI control channel open drain output. Data is shifted out (at the
half BCLK frequency) on the first rising edge of BCLK during the assigned
channels slot. Br is in high impedance state outside the assigned time slot
and during the assigned time slot of a channel if it is disabled.
Bit clock input or output depending of the configuration. When BCLK is an
input, its frequency may be any multiple of 16 KHz from 512 KHz to 6176
KHz.. When BCLK is an output, its frequency is 512 KHz in NT1 auto and
NTRR auto configurations, 1536 KHz in NT/TE configuration; In this case,
BCLK is locked to the recovered clock received from the line. Input or
Output BCLK is synchronous with FSa. Data are shifted in and out (on Bx
and Br) at half the BCLK frequency.
2B+D and GCI control channel input. Data is sampled by the UID on the
second falling edge of BCLK within the period of the bit, during the assigned
channels time slot.
General purpose programmable I/O configured by CR5 register in all non
auto mode configurations.
Input pin to select a transmission test in all auto mode configurations.
TEST1 is associated with TEST2.
General purpose programmable I/O configured by CR5 register in all non
auto mode configurations.
External control output pin in NT1 auto configuration. Normaly high, this pin
is pulled low when an eoc message ”operate 2B+D loopback” is recognized
from the line.
Local febe select:
When tied to 1 the febe is locally looped back. See figure 10.
General purpose programmable I/O configured by CR5 register in all non
auto mode configurations.
External control output pin in LTRR auto configuration. Normaly high, this
pin is pulled low when an ARL command is received by the UID.
External status input pin. In NT1 auto and NTRR auto configurations, this
status is sent on the line through the ps2 bit.
When MO = 0 (LT/NT12 configuration): S2 associated with S0 and S1
selects a GCI channel number on Bx/Br.
When MO = 1: Configuration input pin. Is used associated with CONF1 to
select configuration NT/TE (non auto), NT1 auto, LTRR auto and NTRR
auto.
General purpose programmable I/O configured by CR5 register in all non
auto mode configurations.
External status input pin. In NT1 auto and NTRR auto configurations, this
status is sent on the line through the ps1 bit.
PLL1 can be disabled in LTRR configuration with this pin.
When MO = 0 (LT/NT12 configuration): S1 associated with S0 and S2
selects a GCI channel number on Bx/Br.
When MO = 1: Configuration input pin. Is used associated with CONF2 to
select configuration NT/TE (non auto), NT1 auto, LTRR auto and NTRR
auto.
Description