stlc5412 STMicroelectronics, stlc5412 Datasheet - Page 22

• Manufacturer Part Number: stlc5412
• Description: 2b1q U Interface Device Enhanced With Dect Mode
• Manufacturer: STMicroelectronics

STLC5412
Monitor channel
The Monitor channel is used to write and read all
STLC5412 internal registers. Protocol on the
Monitor channel allows a bidirectional transfer of
bytes between UID and a control unit with ac-
knowledgement at each received byte. Bytes are
transmitted on the Br output and received on the
Bx input in the Monitor channel time slot.
A write or read cycle is always constituted of two
bytes.(see fig. 5). It is possible to operate several
write or read cycles within a single monitor mes-
sage.
Note: Special format is used for EOC channel.
Write cycle
The format to write a message into the UID is:
After the first byte is shifted in, Register address
is decoded. A0 set low indicates a write cycle: the
content of the following received byte has to be
loaded into the addressed register.
A0 set high indicates a read-back cycle request.
The second byte content is not significative.
STLC5412 will respond to the request by sending
back a message with the register content associ-
ated with its own address. It is then possible for
the microprocessor to receive the required regis-
ter content after several other pending messages.
To avoid any loss of data, it is recommended to
operate only one read-back request at a time.
Note: Special format is used for EOC channel.
Read cycle
When UID has a register content to send to the
controller, it send it on the monitor channel di-
rectly. Note that the data to send can be the con-
tent of a Register previously requested by the
controller by means of a read-back request.
The format of the message sent by the UID is:
22/74
A7
D7
A7
D7
A7-A1:
A0:
D7-D0:
D6
D6
A6
A6
A5
D5
A5
D5
Register Address
Write/Read back Indicator
Register Content
A4
D4
2nd byte
A4
D4
2nd byte
1st byte
1st byte
A3
D3
A3
D3
A2
D2
A2
D2
A1
D1
A1
D1
D0
D0
A0
A0
Exchange Protocol
STLC5412 validates a received byte if it is de-
tected two consecutive times identical. (see fig. 5)
The exchange protocol is identical for both direc-
tions. The sender uses the E bit to indicate that it
is sending a Monitor byte while the receiver uses
A bit to acknowledge the received byte.When no
message is transferred, E bit and A bit are forced
to inactive state.
A transmission is started by the sender (Transmit
section of the Monitor channel protocol handler)
by putting the E bit from inactive to active state
and by sending the first byte on Monitor channel
in the same frame. Transmission of a message is
allowed only if A bit sent from the receiver has
been set inactive for at least two consecutive
frames. When the receiver is ready, it validates
the incoming byte when received identical in two
consecutive frames. Then, the receiver set A bit
from the inactive to the active state (preacknowl-
edgement) and maintain active at least in the fol-
lowing frame (acknowledgement).
If validation is not possible (two last bytes re-
ceived are not identical) the receiver aborts the
message by setting the A bit active for only a sin-
gle frame.The second byte can be transmitted by
the sender putting the E bit from the active to the
inactive state and sending the second byte on the
Monitor channel in the same frame . The E bit is
set inactive for only one frame. If it remains inac-
tive more than one frame, it is an end of mes-
sage. The second byte may be transmitted only
after receiving of the pre-acknowledgement of the
previous byte . Each byte has to be transmitted at
least in two consecutive frames.
The receiver validates the current received byte
as for the first one and then set the A bit in the
next two frames first from the active state to the
inactive state (pre-acknowledgement) and back to
the active (acknowledgement). If the receiver can-
not validates the received current byte (two bytes
received not identical)it pre-acknowledges nor-
mally but let the A bit in the inactive state in the
next frame which indicates an abort request . If a
message sent by the UID is aborted, the UID will
send again the complete message until receiving
of an acknowledgement . A message received by
the UID can be acknowledged or aborted with
flow Control.
The most significant bit (MSB) of Monitor byte is
sent first on the Monitor channel. E & A bits are
active low and inactive state on Br is 5 V. When
no byte is transmitted, Monitor channel time slot
A7-A1:
A0:
D7-D0:
Register Address
forced to 0 if spontaneous
interrupt, forced to 1 if read-
back
Register Content