stlc5412 STMicroelectronics, stlc5412 Datasheet - Page 16

• Manufacturer Part Number: stlc5412
• Description: 2b1q U Interface Device Enhanced With Dect Mode
• Manufacturer: STMicroelectronics

STLC5412
Bit Clock BCLK determines the data shift rate on
the Digital Interface. Depending on mode se-
lected, BCLK is an input which may be any multi-
ple of 8 kHz from 256 kHz to 6176 kHz or an out-
put at a frequency depending on the format and
the frequency selected. Possible frequencies are:
Figure 2: DSI Interface formats: MASTER mode.
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256 KHz, 512 KHz, 1536 KHz,
In format 4 the use of 256kHz is forbidden.
BCLK is synchronous with FSa/b frame sync sig-
nal. When output, BCLK is phased locked to the
recovered clock received from the line.
2048 KHz, 2560 KHz.