stlc5412 STMicroelectronics, stlc5412 Datasheet - Page 26

• Manufacturer Part Number: stlc5412
• Description: 2b1q U Interface Device Enhanced With Dect Mode
• Manufacturer: STMicroelectronics

STLC5412
If not programmed this bit is inactive. The relock
will take place only after completion of present
monitor transfer. (EOM received). This locking will
cause a phase jump of FSa and BCLK signals. To
avoid problems on the GCI bus that is synchro-
nized by FSa, a number of 5 GCI frames after the
phase jump will be ignored by the STLC5412.
For proper system operation before writing the
LOCK bit in CR7 register, the MOB bit (Mask
Overhead Bits) in CR4 register should be set to 1
to avoid spontaneous monitor message genera-
tion from STLC5412. Following the relocking the
MOB bit should be set back to desired value after
a minimum time to be defined (ex. 1msec).
The suggestedprocedure is to program the LOCK bit
in CR7 register after the AI indication from
STLC5412. In this case the system controller knows
when the phase jump takes place and can reset the
transmission/receptionof the GCI controller.
TIMING DIAGRAMS FOR DECT
26/74
RX EOC
TX EOC
SFSx
SFSr
SFSx
rxeoc
txeoc
36ms + line delay
12 ms
DECT DECT DECT
DECT DECT DECT
6 ms
LT DECT MODE
RXEOC INT
n*12ms (n=40 minimum)
txeoc
rxeoc
NT DECT MODE
rxeoc
txeoc
6 ms
rxeoc
txeoc
RXEOC INT
Notes:
The DECT EOC message reception generates an
interrupt as a normal EOC message according to
the rules stored in OPR register. The DECT sync
message must be checked 3 times (reset value
of OPR register). If it is not detected 3 times iden-
tical no pulse is generated. The DECT pulse
width on output pin SFSx is 6msec.
MAINTENANCE FUNCTIONS
M channel
In each frame there are 6 ”overhead” bits assigned
to various control and maintenance functions.
Some programmable processing of these bits is
provided on chip while interaction with an external
controller provides the flexibility to take full advan-
tage of the maintenance channels. See OPR,
TXM4, TXM56, TXEOC, RXM4, RXM56, RXEOC
n*12ms
rxeoc
txeoc
rxeoc
txeoc
DECT
DECT
DECT
DECT
DECT
DECT
RXEOC INT
txeoc
rxeoc
txeoc
rxeoc rxeoc
txeoc
RXEOC INT