stlc5412 STMicroelectronics, stlc5412 Datasheet - Page 28

• Manufacturer Part Number: stlc5412
• Description: 2b1q U Interface Device Enhanced With Dect Mode
• Manufacturer: STMicroelectronics

STLC5412
Table 2: 2B1Q Encoding of 2B+ D Fields.
Where:
b
b
b
b
d
q
NOTE: There are 12 2B+D 18-bit fields per 1.5 msec basic frame.
Table 3: Network-to-NT 2B1Q Superframe Technique and Overhead Bit Assignments.
Symbols & Abbreviations:
28/74
NT-to-Network superframe delay offset from Network-to-NT superframe by 60
ms). All bits than the Sync Word are scrambled.
”1”
eoc
SW
ISW inverted synchronization word
s
m
11
18
21
28
1
i
Bit Pair
Quat # (relative)
# Bits
# Quats
= ith quat relative to start of given 18-bit 2B+D data field.
d
Frame
B,C,...
Super
= first bit of B
= last bit of B
= first bit of B
= last bit of B
2
= consecutive D-channel bits (d
#
A
reserve = reserved bit for future standard; set = 1
embedded operations channel
a = address bit
dm = data/message indicator
i = information (data/message)
synchronization word
sign bit (first) in quat
magnitude bit (second) in quat
Data
Quat Positions
Bit Positions
1
I
2
2
octet as received at the S/T interface
octet as received at the S/T interface
octet as received at the S/T interface
octet as received at the S/T interface
Frame
Basic
#
1
2
3
4
5
6
7
8
Time
b
11
q
b
1
12
FRAMING
Word
Sync
1
1-18
ISW
SW
SW
SW
SW
SW
SW
SW
1-9
is first bit of pair as received at the S/T interface)
b
13
q
b
2
14
10-117
19-234
B
2B+D
2B+D
2B+D
2B+D
2B+D
2B+D
2B+D
2B+D
2B+D
2B+D
8
4
I
b
15
q
3
b
16
eoc
eoc
eoc
eoc
118s
eoc
eoc
eoc
eoc
235
M
b
1
dm
dm
17
a1
a1
i3
i6
i3
i6
q
b
4
act
crc
febe far end block error bit (set = 0 for errored
dea
uoa
aib
18
118m
eoc
eoc
eoc
eoc
eoc
eoc
eoc
eoc
236
M
activation bit
cyclic redundancy check: covers 2B+D & M4
1 = most significant bit
2 = next most significant bit
etc
superframe)
deactivation bit (set = 0 to announce deactivation)
u only activation bit (set = 1 to activate S/T)
alarm indication bit (set = 0 to indicate interruption)
b
21
2
a2
a2
q5
i1
i4
i7
i1
i4
i7
b
22
Overhead Bits (M
eoc
eoc
eoc
eoc
eoc
eoc
eoc
eoc
119s
237
b
M
23
3
q
a3
a3
i2
i5
i8
i2
i5
i8
b
6
24
B
8
4
g
119m
b
238
dea
uoa
act
aib
M
25
1
1
1
1
q
4
1-
7
b
M
26
6
2 quats (about 0.75
)
b
120s
crc
239
crc
crc
crc
crc
crc
M
27
1
1
q
5
11
8
b
1
3
5
7
9
28
120m
crc
crc
febe
crc
crc
crc
crc
d
240
M
q
1
D
1
2
1
d
9
6
10
12
2
4
6
8
2