stlc5412 STMicroelectronics, stlc5412 Datasheet - Page 54

• Manufacturer Part Number: stlc5412
• Description: 2b1q U Interface Device Enhanced With Dect Mode
• Manufacturer: STMicroelectronics

STLC5412
Table 9: READ BACK MESSAGES
Notes:
1. For all these registers with the exception of TXEOC, bit 0 of BYTE 1 is set to 1 to indicate read-ba ck message.
2. CR5 configuration/status register is listed with status registers.
3. Bit 7 of BYTE 1 is the first clocked out from the UID.
4. M42x is significant in NT mode only
Table 10: SPONTANEOUS OR DRIVEN MESSAGES
Notes:
1. All status registers can be read by setting first the appropriate command. At any status change, an interrupt cycle is issued.
2. In the RXEOC register:
3. For all These registers with the exception of RXEOC, bit 0 of BYTE 1 is set to 0 to indicate a s tatus register.
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OPR
CR1
CR2
CR3
CR4
CR5
CR6
CR7
TXB1
TXB2
RXB1
RXB2
TXD
RXD
TXM4
TXM56
TXACT
BEC1
BEC2
ECT1
ECT2
TXEOC
IDR
DECTEOC
DBAUD
DTXRX
CR5
STATUS
RXM4
RXM56
RXACT
BEC1
BEC2
RXEOC
FUNCTION
FUNCTION
E = ea1
F = ea2
G = ea3
H = d=0/m = 1
AD7/4
AD7/4
0010
0010
0010
0010
0010
0010
0010
0010
0011
0011
0011
0011
0011
0011
0100
0100
0100
0100
0100
0100
0100
0110
1000
1011
1100
1100
0010
0011
0100
0100
0100
0100
0100
0101
BYTE 1
BYTE 1
AD3/1
AD3/1
CCC
EFG
EFG
EFG
000
001
010
011
100
101
110
111
000
001
010
011
100
101
000
001
010
011
100
101
110
000
001
101
111
000
001
010
011
100
AD0
AD0
H
C
H
H
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
DBAUD7 DBAUD6
XEOC1 XEOC2 XEOC3 XEOC4 XEOC5 XEOC6 XEOC7 XEOC8
DEOC1 DEOC2 DEOC3 DEOC4 DEOC5 DEOC6 DEOC7 DEOC8
DTXRX7
REOC1
ECT17
ECT27
PWDN
M41R
T1SE
SFS
EB1
DX5
DR5
FF1
LB1
CIE
IO4
I04
c7
c7
c7
c7
7
0
0
0
0
0
0
0
0
0
7
0
0
ACTUAT PUPAUT
DTXRX6
REOC2 REOC3
ECT16
ECT26
M42R
M42x
NTS
DX4
DR4
FF0
LB2
EB2
EIE
IO3
I03
c6
c6
c6
c6
6
0
0
0
0
0
0
0
0
6
0
0
0
DBAUD5
DTXRX5
ECT15
ECT25
M43R
B1X5
B2X5
B1R5
B2R5
M43x
DMO
CK2
LBD
DX3
DR3
IO2
FIE
ED
I02
c5
c5
c5
c5
5
0
0
0
0
5
0
0
0
DBAUD4 DBAUD3 DBAUD2 DBAUD1
DTXRX4
REOC4
ECT14
ECT24
M44R
M51R
B1R4
B2R4
B1X4
B2X4
M44x
M51x
OB1
DEN
FFIT
DR2
CK1
DB1
DX2
QM
IO1
I01
c4
c4
c4
c4
4
0
0
0
4
0
0
BYTE 2
BYTE 2
DTXRX3
RxFFU
REOC5
ECT13
ECT23
M45R
M61R
B1R3
B2R3
B1X3
B2X3
M45x
M61x
ESFr
OB0
CK0
ETC
DB2
DX1
DR1
C4R
C4x
AIS
D4
D4
c3
c3
c3
c3
3
0
1
3
DTXRX2
ECT12
ECT22
RxFFO
REOC6 REOC7 REOC8
CTLIO
LOCK
M46R
M52R
TFB0
B1X2
B2X2
B1R2
B2R2
M46x
M52x
DDM
DBD
BP1
DX0
DR0
C3R
0C1
C3x
D3
D3
c2
c2
c2
c2
2
0
2
DTXRX1
PL2EN
ECT11
ECT21
TxFFU
M47R
FEBR
B1R1
B2R1
B1X1
B2X1
FEBx
CMS
MOB
RFS
C2R
SR1
0C0
BP2
TLB
SX1
C2x
D2
D2
c1
c1
c1
c1
1
0
0
1
DBAUD0
DTXRX0
ECT10
ECT20
TxFFO
NEBR
DECT
M48R
B1R0
B2R0
T15D
B1X0
B2X0
M48x
FEBx
BEX
CTC
C1R
C2E
LFS
SX0
SR0
C1x
RR
D1
D1
c0
c0
c0
c0
0
0
0