stlc5412 STMicroelectronics, stlc5412 Datasheet - Page 48

• Manufacturer Part Number: stlc5412
• Description: 2b1q U Interface Device Enhanced With Dect Mode
• Manufacturer: STMicroelectronics

STLC5412
DR5-SR0 Receive D channel Time Slot Assign-
ment
DR5-DR0 and SR1-SR0 bits define the binary
number of the receive D channel time-slot. DR5-
DR0 bits define the binary number of the 8 bits
wide timeslot. Time slot are numbered from 0 to
63. Within this selected time slot., SR1,SR0 bits
define the binary number of the 2 bits wide time-
slot. Sub time-slots are numbered 0 to 3. The reg-
ister content is taken into account at each frame
beginning.
Status Register (STATUS)
(Read only)
After reset: 85H
PWDN Power down
RXFFU RX FIFO underflow
RXFFO: RX FIFO overflow
TXFFU TX FIFO underflow
TXFFO TX FIFO overflow
When one of these four bits is set to 1, Tx FIFO
and/or Rx FIFO is re-adjusted and data is lost. An
interrupt or message is generated if FFIT bit in
CR4 register is set to 1. It is always possible to
read this register by writting STATUS bit = 1 in
RXOH register.
48/74
PWDN X X
PWDN = 1: UID is in power down state
PWDN = 0: UID is in power up state
RXFFU = 1:The bits rate on Br pin is higher than
RXFFU = 0:The bits rate on Br is in accordance
RXFFO = 1:The bits rate on Br pin is lower than
RXFFO = 0:The bits rate on Br pin is in
TXFFU = 1: The bits rate on Bx pin is lower than
TXFFU = 0: The bits rate on Bx pin is in
TXFFO = 1: The bits rate on Bx pin is higher than
TXFFO = 0: The bits rate on Bx pin is in
the bits rate side line.
with the bits rate side line
the bits rate side line.
accordance with the bits rate side
line.
the bits rate side line.
accordance with the bits rate side
line.
the bits rate side line.
accordance with the bits rate side
line.
X RXFFU RXFFO TXFFU TXFFO
Transmit M4 channel Register (TXM4)
After reset: 7DH
When transmitting SL2/SL3 or SN3, the UID shall
continuously send in the M4 channel field the reg-
ister content to the line once per superframe.
Register content is transmitted to the line at each
superframe.
m41
These bits are controlled directly by the on chip
activation encoder-decoder. The corresponding
bits in the TXM4 register are not significant.
m45
(UID performing warm start). Nevertheless, user
can force CSO to 1 by setting m45
When a read back is operated on TXM4, m41x,
m42x in LT, m47x are indicating the current value
of act, dea in LT and uoa/sai bits transmitted to
the line.
Receive spare M4 overhead bits Register
(RXM4) (read only)
After reset: 75H
RXM4 Register is constituted of 8 bits. When the
line is fully activated (super frame synchronized),
STLC5412 extracts the M4 channel bits. m41 is
the act bit; m42 in NT mode is the dea bit; in NT
m47 is the uoa bit; in LT m47 is the sai bit. These
bits are under the control of the activation se-
quencer. No interrupt cycle is provided for the
RXM4 register when a change on one of the acti-
vation bits is detected; never the less, they are
available in RXM4.
When one of the remaining received spare bits is
validated following the criteria selected in the
Configuration Register OPR, the RXM4 register
content is queued in the interrupt register stack, if
no mask overhead bits is set (see MOB bit in CR4
register). It is always possible to read this register
by writting RXM4 bit = 1 in RXOH register.
Transmit M5 and M6 channels Register
(TXM56)
After reset: 1FH
m51
mally equal to 1. Default value can be changed by
setting the respective bits. These bits are trans-
mitted to the line in SL2/SL3 or SN3 signal.
febx Transmit febe bit control
The febe can be forced to 0 by writing 0 in one of
febx if RFS bit in CR6 register is set to 1. The febe bit
set to zero is sent once to the line in the following
available superframe. After febe transmission, febx
m41r m42r m43r m44r m45r m46r m47r m48r
-
-
X
X
X
, m42
, m61
in NT mode is CS0 bit: this is normally 0
m42
-
X
X
X
, m52
m43
in LT, m47
-
X
X
m44
m51
spare over-head bits are nor-
X
X
m45
m61
X
X
X
are activation bits.
m46
m52
X
X
X
to 1.
febx
-
m48
febx
X