stlc5412 STMicroelectronics, stlc5412 Datasheet
stlc5412
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stlc5412 Summary of contents
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... U INTERFACE DEVICE ENHANCED WITH DECT MODE PRELIMINARY DATA PLCC44 ORDERING NUMBER: STLC5412FN Plastic DIP28 ORDERING NUMBER: STLC5412P IDENTIFICATIONCODE AS PERGCISTANDARD DECT FRAME SYNCHRONIZATION EASILY INTERFACEABLE WITH ST5451 (HDLC & GCI CONTROLLER), STLC5464 / STLC5465 AND ANY OTHER GCI, IDL or TDM COMPATIBLE DEVICES ...
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... STLC5412 INDEX DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIN FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . W/DSI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... PIN CONNECTIONS (Top view) PLCC44 MICROWIRE MODE DIP28 MICROWIRE MODE STLC5412 PLCC44 GCI MODE DIP28 GCI MODE 3/74 ...
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... STLC5412 Figure 1: Block Diagram. 4/74 ...
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... NT modes a 15.36 MHz synchronized clock to the system. Scrambling and descrambling are performed as specified in the specifications. On the system side, STLC5412 can be linked to two bus configuration simply by pin MW bias. MICROWIRE( W/DSI) mode (MWpin = 5V): 144 kbit/s 2B+D basic access data is transferred on a multiplex Digital System Interface with 4 different interface formats (see fig ...
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... STLC5412 PIN FUNCTIONS (no Specific Microwire / GCI Mode) Note: all pin number are referred to Plastic DIP28 package. Pin Name In/Out 1, 4 LO+, LO- Out, Out Transmit 2B1Q signal differential outputs to the line transformer. When used with an appropriate 1:1.5 step-up transformer and the proper line interface circuit the line signal conforms to the output specifications in ANSI standard with a nominal pulse amplitude of 2 ...
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... Chip Select input: When this pin is pulled low, data can be shifted in and out from the UID through CI & CO pins. When high, this pin inhibits the MICROWIRE interface. For normal read or write operation, CS has to be pulled low for 16 CCLK periods. STLC5412 Description 7/74 ...
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... STLC5412 PIN FUNCTIONS (specific GCI mode) Pin Name In/Out 6 FSa In Out Input or Output depending of the configuration. FSa KHz clock which indicates the start of the frame on Bx and Br. 7 FSb Out In NT/TE non auto-mode configuration, FSb KHz pulse always indicating the second 64Kbit/sec channel of the frame on Br. ...
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... S0, S1, S2). When pulled high, UID is configured by pins CONF1 and CONF2. MULTIPLE FUNCTION PIN DESCRIPTION Pin 6: FSa Function or In/Out conditions MW(pin MO(pin MW(pin MO(pin Description CMS(cr1 CMS(cr1 CONF2(pin CONF1(pin CONF2(pin CONF1(pin STLC5412 Function In/Ou t FSa Out FSa In FSa Out FSa In FSa Out FSa In 9/74 ...
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... STLC5412 MULTIPLE FUNCTION PIN DESCRIPTION Pin 7: S0/FSb/TEST2 Function or In/Out conditions MW(pin MO(pin MW(pin MO(pin Pin 10: TSR/SCLK/TCLK Function or In/Out conditions MW(pin MO(pin MW(pin MO(pin Pin 12: BCLK Function or In/Out conditions MW(pin MO(pin MW(pin MO(pin 10/74 CMS(cr1 CMS(cr1 CONF1(pin CONF2(pin CONF1(pin CONF2(pin NTS(cr2 NTS(cr2 CONF2(pin ...
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... IO3(cr5 LFS IO3(cr5 IO3(cr5 Function Dx reserved CONF1(pin ES2 IO2(cr5 CONF1(pin IO2(cr5 CONF1(pin CONF1(pin ES2 IO2(cr5 IO2(cr5 STLC5412 In/Ou t Out reserved reserved In In Out In In Out In/Ou t Out reserved Out In Out In In Out In/ reserved In In ...
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... STLC5412 MULTIPLE FUNCTION PIN DESCRIPTION Pin 17: CCLK/S2/CONF2 Function or In/Out conditions MW(pin MO(pin MW(pin MO(pin Pin 18: CI/IO1/ES1/PLLDwith pull up resistor Function or In/Out conditions MW(pin CONF2(pin MO(pin MW(pin CONF2(pin MO(pin Pin 19: CO/S1/CONF1 Function or In/Out conditions MW(pin MO(pin MW(pin MO(pin Pin 22: SFSx/RFS with pull up resistor ...
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... MW(pin Notes: Out OD = Open Drain Output Function ESFR(cr4 SFSr ESFR(cr4 LSD CONF1(pin AIS ESFR(cr4 SFSr CONF1(pin ESFR(cr4 LSD AIS ESFR(cr4 SFSr ESFR(cr4 LSD Function INT RES Function CS MO STLC5412 In/Ou t Out OD Out OD In Out OD Out OD In Out OD Out OD In/Ou t Out OD In In/ 13/74 ...
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... STLC5412 FUNCTIONAL DESCRIPTION Digital Interfaces STLC5412 provides a choice between two types of digital interface for both control data and (2 B+D) basic access data. These are: a) General Circuit Interface: GCI. b) Microwire/Digital System Interface: W/DSI The device will automatically switch to one of them by sensing the MW input pin at the Power up ...
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... When the D chan- nel port is enabled in TDM mode, D bits are as- signed according to the related format on Dx and Dr . STLC5412 provides a choice of four multiplexed formats for the B and D channels data as shown in fig.2 and 3. Format 1: the 2B+D data transfer is assigned to the first 18 bits of the frame on Br and Bx I/0 pins. ...
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... STLC5412 Bit Clock BCLK determines the data shift rate on the Digital Interface. Depending on mode se- lected, BCLK is an input which may be any multi- ple of 8 kHz from 256 kHz to 6176 kHz or an out- put at a frequency depending on the format and the frequency selected. Possible frequencies are: 256 KHz, 512 KHz, 1536 KHz, Figure 2: DSI Interface formats: MASTER mode ...
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... Figure 3: DSI Interface formats: SLAVE mode. STLC5412 17/74 ...
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... The GCI is a standard interface for the intercon- nection of dedicated ISDN components in the dif- ferent equipments of the subscriber loop : In a Terminal, GCI interlinks the STLC5412, the ISDN layer 2 (LAPD) controller and the voice/data processing components as an audio-processor or a Terminal Adaptor module. ...
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... FSa 8 KHz BCLK GCI CHANNEL C Bx/ FSa 8 KHz FSb BCLK MASTER MODE (BCLK = 1.536MHz) GCI CHANNEL 1 GCI CHANNEL C SLAVE MODE 2 FREE MASTER MODE STLC5412 19/74 ...
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... STLC5412 Figure 4c: GCI multiplex examples, (slave mode). 20/74 ...
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... Configuration NT/TE NT1-AUTO LT-RR-AUTO NT-RR-AUTO FSb TEST2 IO1 IO1 ES1 IO2 IO2 ES2 IO3 IO3 EC IO4 IO4 TEST1 SFSx SFSx STLC5412 TEST2 TEST2 PLDD ES1 EC ES2 LFS LFS TEST1 TEST1 RFS RFS 21/74 ...
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... D7-D0: Register Content Exchange Protocol STLC5412 validates a received byte de- tected two consecutive times identical. (see fig. 5) The exchange protocol is identical for both direc- tions. The sender uses the E bit to indicate that it is sending a Monitor byte while the receiver uses A bit to acknowledge the received byte ...
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... EOM (M2) (X) pre-ack ack pre-ack?? pre-ack ack (M2) (M2) (X) (M1) (M1) TWO BYTES MESSAGE - NORMAL TRANSMISSION 2nd byte EOM 3rd byte?? (M2) (or abort ack) (X) pre-ack abort Ready for (M2) (M2) retransmission E & A BITS TIMING STLC5412 X Ready for 1st byte (M1) pre-ack (M1) 23/74 ...
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... The differential line-driver outputs, LO+, LO- are designed to drive a transformer through an external termination circuit. A 1:1.5 trans- former designed as shown in the STLC5412 user guide, results in a signal amplitude of 2.5V pk nominal on the line for single quats of the +3 level. (see output pulse template fig.8). Short-cir- cuit protection is included in the output stage ...
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... DECT EOC message stored in DECT EOC register, generates a pulse on pin SFSx, synchro- nous with next SFSr edge. In this way the STLC5412 provides on pin SFSx a pulse used to resynchronise the DECT frame counter in the base station. The LOCK bit in CR7 register can be used to enable the locking of FSa with SFSr after line is activated ...
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... The suggestedprocedure is to program the LOCK bit in CR7 register after the AI indication from STLC5412. In this case the system controller knows when the phase jump takes place and can reset the transmission/receptionof the GCI controller. TIMING DIAGRAMS FOR DECT ...
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... RXM4 Receive Register or transmitted to on-chip activa- tion sequencer. See OPR, TXM4 and RXM4 reg- isters description for details. STLC5412 When NT1-AUTO or NT-RR-AUTO mode is se- lected, bits ps1 and ps2 in M4 channel are con- trolled directly by biasing input pins ES1 and ES2 respectively ...
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... STLC5412 Table 2: 2B1Q Encoding of 2B+ D Fields. Time Data B I Bit Pair Quat # (relative Bits 8 # Quats 4 Where first bit of B octet as received at the S/T interface last bit of B octet as received at the S/T interface first bit of B octet as received at the S/T interface ...
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... most significant bit 2 = next most significant bit etc febe far end block error bit (set = 0 for errored superframe) sai S/T interface activation indication bit. STLC5412 120s 120m 238 239 240 ...
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... STLC5412 Figure 7: Superframe I/O pin SFS 30/74 ...
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... Figure 8: Normalized output pulse form STLC5412 31/74 ...
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... STLC5412 Figure 9: EOC message processing mode. 32/74 ...
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... Figure 10: CRC Errors Processing (auto-mode) STLC5412 33/74 ...
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... STLC5412 Table 5: EOC message processing: local actions. NT1-AUTO: (eoc address 000 or 111) Message Code Operate 2B+D loopback 0101 0000 Operate B1channel Loopback 0101 0001 Operate B2 channel Loopback 0101 0010 Request Corrupted CRC 0101 0011 Notify of Corrupted CRC 0101 0100 Return to Normal 1111 1111 ...
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... Random Data Transmitted 0 0 Send Single Pulse TURNING ON AND OFF THE DEVICE STLC5412 contains an automatic sequencer for the complete control of the start-up activation se- quences. Interactions with an external control unit requires only Activate Request and Deactivate Request commands, with the option of inserting ...
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... UID provides the GCI clocks needed for control channel transfer; PUP control in- struction is provided to the UID by pulling low the Bx data input; STLC5412 then reacts sending GCI clocks possible to operate an automatic power up of the UID when a wake up tone is detected from the line by connecting the LSD output directly to the Bx input ...
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... RXACT registers are normally associated with the C/I channel (it is possible to associate them with the MONITOR channel thank to the CID bit in STLC5412 CR2 register). All commands and indications are coded on four bits: C1, C2, C3, C4. Codes are listed in Table 7. For each mode, a list of recog- nized commands and generated indications is given ...
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... STLC5412 Table 7a: RXACT (indication) and TXACT (command) codes CODES (GCI or MW, NON AUTO-MODE) RXACT (indications DP/LSD EIU – – – – – ...
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... EI EI – – UAI UAI – – – – – – – – – – – – STLC5412 TXACT (1) RES SP1 RDT EI PDN – – – SP3 AI – AIL DI TXACT (commands) PUP/DR RES – – FA0 – ...
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... STLC5412 (H1), AR instruction forces UID through the ap- propriate sequence to activate the line by sending TN followed by SN1. Beeing in the U-only-active state (H8A), AR command forces the sai bit equal 1 to the line intended to transfer to the net- work an activation attempt at the S/T interface. 1011 (SP3): Send Single Pulse +3 and -3 SP3 test command forces UID to send +3, -3 pulses to the line, one pulse per frame ...
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... For RXACT and TXACT also through C/I channel W/DSI mode, using the MICROWIRE inter- face according to the rules described in section ” W control interface”. Tables 8 and 10 gives the list of all STLC5412 in- ternal registers. Registers are grouped by types and address ar- eas: of ...
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... STLC5412 area 00/0FH: NOP operations. area 10/1FH: test registers: reserved. area 20/2FH: the configuration registers. OPR CR1 CR2 CR3 CR4 CR5 CR6 CR7 Read Write access. CR5 only usefull in GCI mode area 30/3FH: the time slot registers. TXB1 TXB2 RXB1 RXB2 TXD ...
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... Refer to fig. 2 and 3. FF1 FF2 0 0 Format Format Format Format 4 GCI like STLC5412 CK0-CK2 Digital Interface Clock select: ( W/DSI only) CK0-CK2 bits select the BCLK output frequency when DSI clocks are outputs. CK2 CK1 CK0 BCLK frequency 256KHz 0 0 ...
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... STLC5412 SFS = 0: SFSx is an input that synchronizes the transmit superframe. SFS = 1: SFSx is an output indicating the Transmit Superframe mode SFSx is always an output. NTS mode Select. NTS = 0: LT mode selected NTS = 1: NT mode selected DMO D channel Transfer mode Select.( W/DSI only) Significant only when DEN=1 ...
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... After that UID is automatically powered down except if a PUP command is sent to it. of non CTLIO = 0: In master mode and powered down, the UID does not react to an input pin change. MOB Mask Overhead Bits. MOB = 0: No Mask on overhead bit interrupts. STLC5412 45/74 ...
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... STLC5412 MOB = 1: All interrupts issued from RXM4, RXM56 RXEOC and masked still possible to read these registers via RXOH. CTC Corrupted Transmit CRC Control CTC = 0: Allows the normal calculation of the CRC for the transmitted data to the line. CTC = 1: The CRC result transmitted to the line in the next Superframe is inverted ...
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... Configuration register RXD Significant only when format 3 is selected with the D channel selected in multiplexed mode. After reset: W mode 08H (sub time slot 0, time slot 2 se- lected) DR5 DR4 DR3 DR3 DR2 STLC5412 DX0 SX1 SX0 DR1 SR1 SR0 47/74 ...
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... RXM4 Register is constituted of 8 bits. When the line is fully activated (super frame synchronized), STLC5412 extracts the M4 channel bits. m41 is the act bit; m42 in NT mode is the dea bit m47 is the uoa bit m47 is the sai bit. These bits are under the control of the activation se- quencer ...
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... When the line is fully activated (super frame syn- chronized), STLC5412 extracts the overhead bits. When one of the received spare bits m51, m61, m52 is validated following the criterias selected in the Configuration Register OPR. The RXM56 reg- ister content is queued in the interrupt register stack mask overhead bits is set (see MOB bit in CR4 register) ...
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... TXEOC Register is constituted of 12 bits, 3 bits address (EFG), 1 bit data/message Flag (H), 8 bits information (XEOC1 - XEOC8). When trans- mitting SL2/SL3 or SN3 signal. STLC5412 shall continuously send into the EOC channel field the eoc bits twice per superframe. TXEOC register is loaded in the transmit register at each half a su- perframe ...
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... SFSx and SFSr rising edges (total digi- tal delay: tdd ). DBAUD7..DBAUD5: 3 bits to store the internal elastic memory (FIFO) state. The table A shows the coding of the 3-stages elastic memory (elas- tic digital delay: edd). STLC5412 Table A. FIFO state baud delay (edd) 000 -1 ...
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... STLC5412 Table 8: REGISTER ACCESS MESSAGES BYTE 1 FUNCTION AD7/4 AD3/1 AD0 NOP 0000 000 RESERVED 0001 XXX OPR W 0010 000 OPR R 0010 000 CR1 W 0010 001 CR1 R 0010 001 CR2 W 0010 010 CR2 R 0010 010 CR3 W 0010 011 CR3 R 0010 011 CR4 ...
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... Mode B STLC5412 M46x 0 M48x M52x FEBx FEBx C3x C2x C1x RST STATUS ...
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... STLC5412 Table 9: READ BACK MESSAGES BYTE 1 FUNCTION AD7/4 AD3/1 AD0 OPR 0010 000 1 CIE CR1 0010 001 1 FF1 CR2 0010 010 1 SFS CR3 0010 011 1 LB1 CR4 0010 100 1 EB1 CR5 0010 101 1 CR6 0010 110 1 T1SE CR7 0010 111 1 TXB1 ...
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... Great care must be taken in the layout of the printed cir- cuit board in order to preserve the high transmis- sion performance of the STLC5412. To maximize performance, do not use the philosophy of separat- ing analog and digital grounds for chip. All GND ...
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... STLC5412 Figure 12: Recommended connections. 56/74 ...
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... Figure 13a: LT Application. STLC5412 57/74 ...
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... STLC5412 Figure 13b: LT Application. 58/74 ...
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... Figure 13c: RR Application. STLC5412 59/74 ...
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... STLC5412 APPENDIX A - STATE MATRIX 60/74 ...
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... STLC5412 61/74 ...
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... STLC5412 APPENDIX B - ELECTRICAL PARAMETERS ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Supply Voltage CC V Input Voltage IN T Operating Temperature Range A T Storage Temperature Range stg TRANSMISSION ELECTRICAL PARAMETERS Parameter LINE INTERFACE FEATURES Power up Output Differential Impedance (0–20KHz) between LO+/LO- Power Down Output Differential Impedance (0–20KHz) between LO+/LO- ...
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... Measured from Measured from Measured from 200 25 25 Out First Bit on CO Load = 2LSTTL Loads Load = 80pF + 2LSTTL Loads STLC5412 Max. Unit MHz +100 ppm 50 ns pk- 4095 KHz 6144 KHz ...
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... STLC5412 Figure 14: BCLK, FSA, FSB, SLAVE MODE, DELAYED MODE, FORMATS ONLY). Figure 15: BCLK, FSA, FSB, SLAVE MODE, NON DELAYED MODE, FORMATS ONLY). 64/74 ...
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... THE FRAME Note 1: in accordance to the selected frequency. High level duration - Low level duration t t DBF DBF t DBF SECOND BIT SEVENTH BIT FIRST BIT OF OF THE OF THE THE FRAME FRAME FRAME STLC5412 DBF DBF DBF EIGHT BIT OF THE FRAME D96TL253 65/74 ...
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... STLC5412 Figure 18: BCLK, FSA, FSB, MASTER MODE, NON DELAYED MODE, FORMATS ONLY). Figure 19: BCLK, FSA, FSB, MASTER MODE, FORMAT 4 ALWAYS NON DELAYED MODE AND GCI MODE). 66/74 ...
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... Figure 20: BX, DX, BR, DR, SLAVE & MASTER, DELAYED & NON DELAYED, FORMATS ONLY) Figure 21: BX, DX, BR, DR, SLAVE & MASTER, FORMAT 4 ALWAYS NON DELAYED & GCI MODE STLC5412 67/74 ...
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... STLC5412 Figure 22: SPECIAL CASE BR, DR, ONLY FIRST BIT OF THE FRAME, IN SLAVE AND NON DE- LAYED MODES FORMATS 1 3 (MW MODE), FORMAT & GCI MODE) Figure 23: TSRB, SLAVE & MASTER, DELAYED & NON DELAYED, FORMATS ONLY) 68/74 24 ...
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... Figure 24: TSRB, SLAVE & MASTER, FORMAT 4 ALWAYS NON DELAYED MODE ( W & GCI) Figure 25: SPECIAL CASE TSRB FIRST CHANNEL OF THE FRAME, IN SLAVE & NON DELAYED MODE, FORMATS 1 3 (MW MODE), FORMAT & GCI MODE) 25 STLC5412 69/74 ...
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... STLC5412 Figure 26: DCLK, DX CONTINUOUS MODE SLAVE & MASTER, DELAYED & NON DELAYED MODES ALL FORMATS IN W MODE ONLY Figure 27: MCLK ALL MODES Figure 28: W PORT Mode A 70/74 ...
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... Figure 29: W PORT Mode B STLC5412 71/74 ...
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... STLC5412 mm inch DIM. MIN. TYP. MAX. MIN. TYP. A 17.4 17.65 0.685 B 16.51 16.65 0.650 C 3.65 3.7 0.144 D 4.2 4.57 0.165 d1 2.59 2.74 0.102 d2 0.68 0.027 E 14.99 16 0.590 e 1.27 0.050 e3 12.7 0.500 F 0.46 0.018 F1 0.71 0.028 G 0.101 M 1.16 0.046 M1 1.14 0.045 72/74 OUTLINE AND MECHANICAL DATA MAX. 0.695 0.656 0.146 0.180 0.108 0.630 0.004 PLCC44 ...
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... DIM. MIN. TYP. MAX. MIN. TYP. a1 0.63 0.025 b 0.45 0.018 b1 0.23 0.31 0.009 b2 1.27 0.050 D 37.34 E 15.2 16.68 0.598 e 2.54 0.100 e3 33.02 1.300 F 14.1 I 4.445 0.175 L 3.3 0.130 OUTLINE AND MECHANICAL DATA MAX. 0.012 1.470 0.657 0.555 DIP28 STLC5412 73/74 ...
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... Human Body Model (MIL-STD 883 Method 3015): with C = 100pF 1500 and GND. Device characterization showed that, in front of the SGS-THOMSON Internaly Quality Standards, all pins of STLC5412 withstand at least 2000V. The above points are not expected to represent a pratical limit for the correct device utilization nor for its reliability in the field. Nonetheless they must be mentionned in connection with the applicability of the different SURE 6 requirements to STLC5412 ...