s908az32ag2cfue Freescale Semiconductor, Inc, s908az32ag2cfue Datasheet - Page 79

• Manufacturer Part Number: s908az32ag2cfue
• Description: M68hc08 Microcontrollers 8-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

7.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of
external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles
(see
or POR (see
during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the
falling edge of RST shown in
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
7.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out
4096 CGMXCLK cycles. Another sixty-four CGMXCLK cycles later, the CPU and memories are released
from reset to allow the reset vector sequence to occur. See
At power-on, the following events occur:
Freescale Semiconductor
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Figure
A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables CGMOUT.
Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow
stabilization of the oscillator.
The RST pin is driven low during the oscillator stabilization time.
The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are
cleared.
7-5). An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI,
Figure
CGMXCLK
IRST
RST
IAB
7-6). Note that for LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles
Figure
Figure 7-6. Sources of Internal Reset
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
RST PULLED LOW BY MCU
Figure 7-5. Internal Reset Timing
MC68HC908AZ32A Data Sheet, Rev. 2
7-5.
COPRST
32 CYCLES
POR
LVI
INTERNAL RESET
Figure
32 CYCLES
7-7.
VECTOR HIGH
Reset and System Initialization
79