s908az32ag2cfue Freescale Semiconductor, Inc, s908az32ag2cfue Datasheet - Page 192

• Manufacturer Part Number: s908az32ag2cfue
• Description: M68hc08 Microcontrollers 8-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Timer Interface Module A (TIMA)
PTF2/TCH4 pin. Writing to the TIMA channel 5 registers enables the TIMA channel 5 registers to
synchronously control the output after the TIMA overflows. At each subsequent overflow, the TIMA
channel registers (4 or 5) that control the output are the ones written to last. TASC4 controls and monitors
the buffered output compare function and TIMA channel 5 status and control register (TASC5) is unused.
While the MS4B bit is set, the channel 5 pin, PTF3/TCH5, is available as a general-purpose I/O pin.
18.3.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIMA can generate a PWM
signal. The value in the TIMA counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIMA counter modulo registers. The time
between overflows is the period of the PWM signal.
As
of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIMA
to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIMA to
set the pin if the state of the PWM pulse is logic 0.
The value in the TIMA counter modulo registers and the selected prescaler output determines the
frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIMA counter modulo registers produces a PWM period of 256 times the internal bus
clock period if the prescaler select value is $000 (see
The value in the TIMA channel registers determines the pulse width of the PWM output. The pulse width
of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIMA channel registers
produces a duty cycle of 128/256 or 50%.
18.3.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as described in
Modulation
pulse width value over the value currently in the TIMA channel registers.
192
Figure 18-3
(PWM). The pulses are unbuffered because changing the pulse width requires writing the new
PTEx/TCHx
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. Writing to the active
channel registers is the same as generating unbuffered output compares.
shows, the output compare value in the TIMA channel registers determines the pulse width
OVERFLOW
Figure 18-3. PWM Period and Pulse Width
PULSE
WIDTH
PERIOD
MC68HC908AZ32A Data Sheet, Rev. 2
COMPARE
OUTPUT
OVERFLOW
NOTE
18.8.1 TIMA Status and Control
COMPARE
OUTPUT
OVERFLOW
Freescale Semiconductor
COMPARE
OUTPUT
18.3.4 Pulse Width
Register).