s908az32ag2cfue Freescale Semiconductor, Inc, s908az32ag2cfue Datasheet - Page 106

• Manufacturer Part Number: s908az32ag2cfue
• Description: M68hc08 Microcontrollers 8-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Clock Generator Module (CGM)
8.9.4 Reaction Time Calculation
The actual acquisition and lock times can be calculated using the equations below. These equations yield
nominal values under the following conditions:
The K factor in the equations is derived from internal PLL parameters. K
is configured in acquisition mode, and K
(See
Note the inverse proportionality between the lock time and the reference frequency.
In automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the
reference frequency. (See
clock cycles, n
before exiting acquisition mode. A certain number of clock cycles, n
PLL is within the lock mode entry tolerance, Δ
multiple of n
Also, since the average frequency over the entire measurement period must be within the specified
tolerance, the total time usually is longer than t
In manual mode, it is usually necessary to wait considerably longer than t
clock (see
Influences on Reaction
When defining a limit in software for the maximum lock time, the value must allow for variation due to all
of the factors mentioned in this section, especially due to the C
influences.
The calculated lock time is only an indication and it is the customer’s responsibility to allow enough of a
guard band for their application. Prior to finalizing any software and while determining the maximum lock
time, take into account all device to device differences. Typically, applications set the maximum lock time
as an order of magnitude higher than the measured value. This is considered sufficient for all such device
to device variation.
Freescale recommends measuring the lock time of the application system by utilizing dedicated software,
running in FLASH, EEPROM or RAM. This should toggle a port pin when the PLL is first configured and
switched on, then again when it goes from acquisition to lock mode and finally again when the PLL lock
106
•
•
•
•
8.3.2.2 Acquisition and Tracking
Correct selection of filter capacitor, C
Room temperature operation
Negligible external leakage on CGMXFC
Negligible noise
8.3.3 Base Clock Selector
ACQ
ACQ
/f
CGMRDV
, is required to ascertain that the PLL is within the tracking mode entry tolerance, Δ
Time, may slow the lock time considerably.
, and the acquisition to lock time, t
8.3.2.3 Manual and Automatic PLL Bandwidth
MC68HC908AZ32A Data Sheet, Rev. 2
Circuit), because the factors described in
Modes).
t
acq
t
trk
al
is the K factor when the PLL is configured in tracking mode.
t
=
=
Lock
F
(see
Lock
⎛
⎝
Lock
⎛
⎝
------------------- -
f
------------------- -
f
CGMRDV
CGMRDV
=
V
. Therefore, the acquisition time, t
V
8.9.3 Choosing a Filter
as calculated above.
DDA
DDA
t
ACQ
⎞
⎠
⎞
⎠
+
⎛
⎝
⎛
⎝
AL
----------- -
K
------------ -
K
t
AL
, is an integer multiple of n
TRK
4
ACQ
F
8
capacitor and application specific
⎞
⎠
⎞
⎠
TRK
, is required to ascertain that the
acq
Lock
Modes). A certain number of
Capacitor).
is the K factor when the PLL
before selecting the PLL
8.9.2 Parametric
Freescale Semiconductor
ACQ
, is an integer
TRK
/f
CGMRDV
TRK
.
,