s908az32ag2cfue Freescale Semiconductor, Inc, s908az32ag2cfue Datasheet - Page 251

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s908az32ag2cfue

Manufacturer Part Number
s908az32ag2cfue
Description
M68hc08 Microcontrollers 8-bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
23.5.2 Data Direction Register D
Data direction register D determines whether each port D pin is an input or an output. Writing a logic 1 to
a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer.
DDRD[7:0] — Data Direction Register D Bits
Figure 23-13
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a
logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
Freescale Semiconductor
These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins
as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
shows the port D I/O logic.
Address:
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
DDRD
Reset:
Read:
Bit
Write:
0
1
READ DDRD ($0007)
WRITE DDRD ($0007)
WRITE PTD ($0003)
READ PTD ($0003)
DDRD7
$0007
PTD
Bit 7
Bit
X
X
0
Figure 23-12. Data Direction Register D (DDRD)
DDRD6
Input, Hi-Z
I/O Pin
Output
Mode
6
0
Table 23-4. Port D Pin Functions
RESET
Figure 23-13. Port D I/O Circuit
MC68HC908AZ32A Data Sheet, Rev. 2
DDRD5
5
0
Accesses to
Table 23-4
Read/Write
DDRD[7:0]
DDRD[7:0]
DDRD
NOTE
DDRD4
DDRDx
PTDx
4
0
summarizes the operation of the port D pins.
DDRD3
3
0
PTD[7:0]
Read
Pin
DDRD2
Accesses to PTD
2
0
DDRD1
PTD[7:0]
1
0
PTD[7:0]
Write
DDRD0
(1)
Bit 0
PTDx
0
Port D
251

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