s908az32ag2cfue Freescale Semiconductor, Inc, s908az32ag2cfue Datasheet - Page 320

• Manufacturer Part Number: s908az32ag2cfue
• Description: M68hc08 Microcontrollers 8-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Glossary
software interrupt (SWI) — An instruction that causes an interrupt and its associated vector fetch.
SPI — See "serial peripheral interface module (SPI)."
stack — A portion of RAM reserved for storage of CPU register contents and subroutine return
stack pointer (SP) — A 16-bit register in the CPU08 containing the address of the next available storage
start bit — A bit that signals the beginning of an asynchronous serial transmission.
status bit — A register bit that indicates the condition of a device.
stop bit — A bit that signals the end of an asynchronous serial transmission.
subroutine — A sequence of instructions to be used more than once in the course of a program. The last
synchronous — Refers to logic circuits and operations that are synchronized by a common reference
TIM — See "timer interface module (TIM)."
timer interface module (TIM) — A module used to relate events in a system to a point in time.
timer — A module used to relate events in a system to a point in time.
toggle — To change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0.
tracking mode — Mode of low-jitter PLL operation during which the PLL is locked on a frequency. Also
two’s complement — A means of performing binary subtraction using addition techniques. The most
unbuffered — Utilizes only one register for data; new data overwrites current data.
unimplemented memory location — A memory location that is not used. Writing to an unimplemented
V —The overflow bit in the condition code register of the CPU08. The CPU08 sets the V bit when a two's
variable — A value that changes during the course of program execution.
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addresses.
location on the stack.
instruction in a subroutine is a return from subroutine (RTS) instruction. At each place in the main
program where the subroutine instructions are needed, a jump or branch to subroutine (JSR or
BSR) instruction is used to call the subroutine. The CPU leaves the flow of the main program to
execute the instructions in the subroutine. When the RTS instruction is executed, the CPU returns
to the main program where it left off.
signal.
see "acquisition mode."
significant bit of a two’s complement number indicates the sign of the number (1 indicates
negative). The two’s complement negative of a number is obtained by inverting each bit in the
number and then adding 1 to the result.
location has no effect. Reading an unimplemented location returns an unpredictable value.
Executing an opcode at an unimplemented location causes an illegal address reset.
complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the
overflow bit.
MC68HC908AZ32A Data Sheet, Rev. 2
Freescale Semiconductor