s908az32ag2cfue Freescale Semiconductor, Inc, s908az32ag2cfue Datasheet - Page 183

• Manufacturer Part Number: s908az32ag2cfue
• Description: M68hc08 Microcontrollers 8-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

SPRF — SPI Receiver Full Bit
ERRIE — Error Interrupt Enable Bit
OVRF — Overflow Bit
MODF — Mode Fault Bit
SPTE — SPI Transmitter Empty Bit
Freescale Semiconductor
This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data
register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status and control register
with SPRF set and then reading the SPI data register. Any read of the SPI data register clears the
SPRF bit.
Reset clears the SPRF bit.
This read-only bit enables the MODF and OVRF flags to generate CPU interrupt requests. Reset
clears the ERRIE bit.
This clearable, read-only flag is set if software does not read the byte in the receive data register before
the next byte enters the shift register. In an overflow condition, the byte already in the receive data
register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI
status and control register with OVRF set and then reading the SPI data register. Reset clears the
OVRF flag.
This clearable, read-only flag is set in a slave SPI if the SS pin goes high during a transmission. In a
master SPI, the MODF flag is set if the SS pin goes low at any time. Clear the MODF bit by reading
the SPI status and control register with MODF set and then writing to the SPI data register. Reset
clears the MODF bit.
This clearable, read-only flag is set each time the transmit data register transfers a byte into the shift
register. SPTE generates an SPTE CPU interrupt request if the SPTIE bit in the SPI control register is
set also.
1 = Receive data register full
0 = Receive data register not full
1 = MODF and OVRF can generate CPU interrupt requests
0 = MODF and OVRF cannot generate CPU interrupt requests
1 = Overflow
0 = No overflow
1 = SS pin at inappropriate logic level
0 = SS pin at appropriate logic level
Address:
Do not write to the SPI data register unless the SPTE bit is high.
Reset:
Read:
Write:
Figure 17-13. SPI Status and Control Register (SPSCR)
$0011
SPRF
Bit 7
R
0
= Reserved
ERRIE
6
0
MC68HC908AZ32A Data Sheet, Rev. 2
OVRF
5
0
NOTE
MODF
4
0
= Unimplemented
SPTE
3
1
MODFEN
2
0
SPR1
1
0
SPR0
Bit 0
0
I/O Registers
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