s908az32ag2cfue Freescale Semiconductor, Inc, s908az32ag2cfue Datasheet - Page 214

• Manufacturer Part Number: s908az32ag2cfue
• Description: M68hc08 Microcontrollers 8-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Timer Interface Module B (TIMB)
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
19.7 I/O Signals
Port D shares one of its pins with the TIMB. Port F shares two of its pins with the TIMB. PTD4/ATD12 is
an external clock input to the TIMB prescaler. The two TIMB channel I/O pins are PTF4 and PTF5/TBCH1.
19.7.1 TIMB Clock Pin (PTD4/ATD12)
PTD4/ATD12 is an external clock input that can be the clock source for the TIMB counter instead of the
prescaled internal bus clock. Select the PTD4/ATD12 input by writing logic 1s to the three prescaler select
bits, PS[2:0]
TCLK
The maximum TCLK frequency is the least: 4 MHz or bus frequency ÷ 2.
PTD4/ATD12 is available as a general-purpose I/O pin or ADC channel when not used as the TIMB clock
input. When the PTD4/ATD12 pin is the TIMB clock input, it is an input regardless of the state of the
DDRD4 bit in data direction register D.
19.7.2 TIMB Channel I/O Pins (PTF5/TBCH1–PTF4)
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
PTF4 and PTF5/TBCH1 can be configured as buffered output compare or buffered PWM pins.
19.8 I/O Registers
These I/O registers control and monitor TIMB operation:
19.8.1 TIMB Status and Control Register
The TIMB status and control register:
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HMIN
TIMB status and control register (TBSC)
TIMB control registers (TBCNTH–TBCNTL)
TIMB counter modulo registers (TBMODH–TBMODL)
TIMB channel status and control registers (TBSC0 and TBSC1)
TIMB channel registers (TBCH0H–TBCH0L, TBCH1H–TBCH1L)
Enables TIMB overflow interrupts
Flags TIMB overflows
Stops the TIMB counter
Resets the TIMB counter
Prescales the TIMB counter clock
, is:
19.8.1 TIMB Status and Control
MC68HC908AZ32A Data Sheet, Rev. 2
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bus frequency
Register. The minimum TCLK pulse width, TCLK
1
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Freescale Semiconductor
LMIN
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